test007.v
2.26 KB
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//
// test007 Test of sequential down DMA read/write commands
//
task test007;
fork
test007_check;
test007_cmddata;
join
endtask
task test007_check;
begin
check_unmasked("test007");
check_nosubblock("test007");
check_single("test007");
end
endtask
task test007_cmddata;
reg [CBUS_DATA_SIZE-1:0] address;
reg [DBUS_DATA_SIZE-1:0] expected_d_data, actual_d_data;
reg [EBUS_DATA_SIZE-1:0] expected_e_data, actual_e_data;
integer i, j;
//
// Write a set of addresses using the (nonsequential) down mode
//
begin
address = 0;
for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
begin
for (j = 0; j < i; j = j + 1)
begin
address = address + 8;
end
end
address = address - 8;
for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
begin
cbus_dma_write(`DMA_UNMASKED, `DMA_DOWN, address,
BUS_DEVICE_MI, -2, i*8);
while (!dma_start)
@(posedge clock);
for (j = 0; j < i; j = j + 1)
begin
dbus_data_out <= {2{address}};
ebus_data_out <= address[10:3];
@(posedge clock);
address = address - 8;
end
end
//
// Read back and verify these addresses in (nonsequential) down mode
//
address = 0;
for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
begin
for (j = 0; j < i; j = j + 1)
begin
address = address + 8;
end
end
address = address - 8;
for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
begin
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_DOWN, address, BUS_DEVICE_MI, 3, i*8);
while (!dma_start)
@(posedge clock);
for (j = 0; j < i; j = j + 1)
begin
check_data("test007", {2{address}}, dbus_data_reg,
address[10:3], ebus_data_reg);
@(posedge clock);
address = address - 8;
end
end
//
// Read back and verify these addresses in (sequential) up mode
//
address = 0;
for (i = 1; i <= `MAX_TRANSFER; i = i + 1)
begin
for (j = 0; j < i; j = j + 1)
begin
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, address, BUS_DEVICE_MI, 3, 8);
dbus_get_data(actual_d_data, actual_e_data, 3);
expected_d_data = {2{address}};
expected_e_data = address[10:3];
check_data("test007", expected_d_data, actual_d_data,
expected_e_data, actual_e_data);
address = address + 8;
end
end
end
endtask