/*
 * Copyright (C) 1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * Copyright (C) 1998 Digital Equipment Corporation
 *
 * This file is part of the SimOS distribution.
 * See LICENSE file for terms of the license.
 *
 */


/* *********************************************************
 * Speculative EV5 trap architecture simulator
 * *********************************************************/

#include <alpha/fpu.h>
#include <strings.h>
#include "simtypes.h"
#include "sim_error.h"
#include "alpha.h"
#include "alpha_params.h"
#include "ev5_ipr.h"
#include "ipr_decode.h"
#include "machine_params.h"
#include "cpu_interface.h"
#include "tb.h"
#include "qc.h"
#include "ev5.h"
#include "alpha_trace.h"
#include "hw_events.h"

#include "external_trace.h"

#define NT_MODE(_p) ((_p)->ipr[IPR_MCSR]&0x2) 


/* *******************************************************
 * Locked registres. Only updated by HW after SW
 * read. (HRM page 5-46)
 * *******************************************************/

#define LOCKED_REGISTER_MMSTAT  (1<<0)
#define LOCKED_REGISTER_VA_FORM (1<<1)
#define LOCKED_REGISTER_VA      (1<<2)

void EV5_Trap(AlphaState *P, int trap); 
static void SetMM_Stat(AlphaState  *P,Reg flags, VA);
static void SetIMM_Stat(AlphaState  *P,Reg flags, VA);

AlphaTrapState *allocTrapState(AlphaTrapState *oldTrapState)
{
   AlphaTrapState *nts = (AlphaTrapState*)malloc(sizeof(AlphaTrapState));
   ASSERT(nts != NULL);
   if (oldTrapState != NULL)
      bcopy((const char*)oldTrapState, (char*)nts, sizeof(AlphaTrapState));
   else
      bzero((char*)nts, sizeof(AlphaTrapState));
   nts->prev = oldTrapState;
   return nts;
}
 
AlphaTrapState *initTrapState(AlphaTrapState *nts, AlphaTrapState *oldTrapState)
{
   ASSERT(nts != NULL);
   if (oldTrapState != NULL)
      bcopy((const char*)oldTrapState, (char*)nts, sizeof(AlphaTrapState));
   else
      bzero((char*)nts, sizeof(AlphaTrapState));
   nts->prev = oldTrapState;
   return nts;
}

void freeTrapState(AlphaTrapState *trapState)
{
   free((char *)trapState);
}

/* ************************************************************
 * EV5_InitPE. 
 * **********************************************************/

extern void EV5_InitPE(AlphaState *pe, int cpuNum)
{
   bzero((char*)pe,sizeof(AlphaState));
   pe->myNum = cpuNum;
   pe->PC = PAL_BASE|TRAP_RESET;

   pe->takeInterrupt = 1;
   pe->ipr = (Reg*)malloc(MAX_IPR*sizeof(Reg));
   bzero((char*)pe->ipr,MAX_IPR*sizeof(Reg));
   pe->ipr[IPR_PAL_BASE] = PAL_BASE;
      
   pe->trapState = allocTrapState(pe->trapState);

   pe->tb = TBInit(); 
   EV5_UpdateQCMode(pe,TB_INSTR);
   EV5_UpdateQCMode(pe,TB_DATA);
   pe->cpuState = cpu_not_booted;
   pe->takeInterruptAtRei = 1; /* epsilon might turn it off */

}

/* ************************************************************
 * EV5_CheckForInterrupts. 
 * This only partially implements the interrupt architecture
 * of the machine. 
 * **********************************************************/

int EV5_CheckForInterrupts(AlphaState *P, const char *where)
{
   Reg *ipr = P->ipr;
   Reg summary = 0;
   Reg targetIPL = 0;

   if (IS_PAL(P)) {
      return 0;
   }

   /* 
    * software interrupts
    */

   if (ipr[IPR_SIRR]) {
      int i;
      for ( i=INTLEVEL_SOFTWARE_MIN;i<INTLEVEL_SOFTWARE_MAX;i++) {
         if (ipr[IPR_SIRR] & (1LL<<i)) {
             /* See table 4-19 of 21164 hardware reference */
             targetIPL = (i - INTLEVEL_SOFTWARE_MIN) + 1;
             summary |= (1LL<<i);
         }
      }
   }
   
   /*
    * external interrupts 
    */

   if (P->pending_irq) {
      int i;
      for( i=INTLEVEL_EXTERNAL_MIN;i<INTLEVEL_EXTERNAL_MAX;i++) {
	 if (P->pending_irq &(1LL<<i)) {
             /* See table 4-19 of 21164 hardware reference */
            targetIPL = i;
	    summary |= (1LL<<i);
	 }
      }
   }

   if (ipr[IPR_ASTSR]) {
      CPUError("ev5.c:Asynchronous traps not impl. \n");
   }

   if (!targetIPL) return 0;

   if (targetIPL > P->trapState->atr[ATR_IPL]) {
      /*
       *take interrupt. Maybe we should delay until unstall when
       * we get caches. XXX
       */
      P->trapState->atr[ATR_ISR] = summary;
      P->trapState->atr[ATR_INTID] = targetIPL;

      if (alphaDebugParams.debugInterrupts)
         CPUWarning("EV5_CheckForInterrupts %s: INTERRUPT cycle=%ld summary=0x%lx targetIPL=%d IPL=%d PS=0x%lx PC=0x%lx RA=0x%lx \n",
                    where,
                    CPUVec.CycleCount(P->myNum),
                    summary, targetIPL, P->trapState->atr[ATR_IPL], ipr[IPR_PS],
                    P->PC, P->reg[REG_RA]);
 
      EV5_Trap(P,TRAP_INTERRUPT);
      return 1;
   } else {
#if 0
      CPUWarning("interrupt summary 0x%lx targetIPL %d ipl %d ps 0x%lx\n",
		 summary, targetIPL, P->trapState->atr[ATR_IPL], ipr[IPR_PS]); 
#endif

      return 0;
   }
}

int EV5_SetExtInterrupt(AlphaState *P, int irq)
{
   ASSERT( irq >=INTLEVEL_EXTERNAL_MIN &&irq < INTLEVEL_EXTERNAL_MAX);
   P->pending_irq_count[irq]++;
   P->pending_irq |= 1LL<<irq;
   if (alphaDebugParams.debugInterrupts)
      CPUWarning("EV5_SetExtInterrupt: cycle=%ld cpu=%d pc=%lx IRQ=%d pending_irq=%lx pirq_cnt=%d IPL=%d IS_PAL=%d\n",
                 CPUVec.CycleCount(P->myNum), P->myNum, P->PC, irq, 
                 P->pending_irq, P->pending_irq_count[irq], 
                 P->trapState->atr[ATR_IPL],
                 IS_PAL(P));
   if (P->takeInterrupt)
      return EV5_CheckForInterrupts(P, "EV5_SetExtInterrupt");
   else
      return 0;
}

void EV5_ClearExtInterrupt(AlphaState *P, int irq)
{
   ASSERT( irq >=INTLEVEL_EXTERNAL_MIN && irq < INTLEVEL_EXTERNAL_MAX);
   P->pending_irq_count[irq]--;
   ASSERT(P->pending_irq_count[irq]>=0);
   if (alphaDebugParams.debugInterrupts)
      CPUWarning("EV5_ClearExtInterrupt: cycle=%ld cpu=%d pc=%lx IRQ=%d pending_irq=%lx pirq_cnt=%d IPL=%d IS_PAL=%d\n",
                 CPUVec.CycleCount(P->myNum), P->myNum, P->PC, irq, 
                 P->pending_irq, P->pending_irq_count[irq], 
                 P->trapState->atr[ATR_IPL],
                 IS_PAL(P));
   if (P->pending_irq_count[irq]==0) { 
      P->pending_irq &= ~(1LL<<irq);
   }
}

/* *************************************************************
 * EV5_ITranslateVirtual 
 * *************************************************************/

MMUStatus  EV5_ITranslateVirtual(AlphaState *P, PA *pAddr, int trapNow)
{
   VA vA = P->PC;
   Reg_s check;
   Reg vpfn;
   struct TBEntry *tb;
   if (IS_PAL(P)) {
      /*
       * that's wierd. It appears that the
       * PC holds a physical address at this point
       */
      *pAddr = P->PC & ~0x3;
      return MMU_SUCCESS;
   }
   /*
    * check sign extension 
    */
   check = vA;
   if (check < 0) { 
      ASSERT( (check&~VA_MASK)==~VA_MASK);
   } else { 
      ASSERT ((vA & VA_MASK)==vA); 
   }
   vpfn = VADDR2TAG(vA);

   if (((vA>>41)&3)==2 && ISP_ISP1ENABLED(P->ipr) ) {
      *pAddr = ALIGN4(vA & PA_MASK);
      if (ISP_SP1EXECUTE(P->ipr)) {
         QCInsert(P->curIQC,P->myNum,vpfn,*pAddr,0);
         return MMU_SUCCESS;
      } else {
         CPUError("%ld ev5:: CPU in %d mode for KSEG ref pc=0x%lx\n",
                  CPUVec.CycleCount(P->myNum),CURRENT_MODE(P),P->PC);
         if (trapNow) {
            SetIMM_Stat(P,0,vA);
            EV5_Trap(P,TRAP_ITB_ACV);
         }
         return MMU_EXCEPTION;
      }
      
   }
   if (((vA>>30)&0x1fff)==0x1ffe &&  ISP_ISP0ENABLED(P->ipr)) {
      *pAddr = ALIGN4(vA & BITMASK(30));
      if (ISP_SP0EXECUTE(P->ipr)) {
         QCInsert(P->curIQC,P->myNum,vpfn,*pAddr,0);
         return MMU_SUCCESS;
      } else {
         if (trapNow) {
            SetIMM_Stat(P,0,vA);
            EV5_Trap(P,TRAP_ITB_ACV);
         }
         return MMU_EXCEPTION;
      }
   }
   
   tb = TBLookup(P->tb,TB_INSTR,VADDR2TAG(vA), ISP_CURRENT_IASN(P->ipr));
   if (tb) {
      int gh  = tb->gh;
      Reg pfn = tb->pfn;
      Reg xre = tb->xre;
      Reg mask = pfn & ~BITMASK(gh*3);
      VA offset = vA & BITMASK(13+gh*3);
      *pAddr = PAGE2ADDR(mask) | offset;
      
      if ((*pAddr) >>(PA_BITS-1) !=0) {
         /* I/O stuff. fail */
         ASSERT(0);
      }
      if (xre & ISP_ITLBPROT(P->ipr)) {
         QCInsert(P->curIQC,P->myNum,vpfn,*pAddr,0);
         return MMU_SUCCESS;
      } else {
         if (trapNow) {
            SetIMM_Stat(P,0,vA);
            EV5_Trap(P,TRAP_ITB_ACV);
         }
         return MMU_EXCEPTION;
      }
   }
#ifdef DEBUG_EV5
   CPUWarning("%10ld ITLB-miss pc=0x%lx \n",CPUVec.CycleCount(P->myNum),P->PC);
#endif
   if (trapNow) {
      SetIMM_Stat(P,0,vA);
      EV5_Trap(P,TRAP_ITB_MISS);
   }
   return MMU_EXCEPTION;
}



/* *************************************************************
 * EV5_DTranslateVirtual 
 * *************************************************************/

MMUStatus EV5_DTranslateVirtual(AlphaState *P, VA vA, int isWrite, int trapNow, PA *pAddr)
{
   Reg vpfn;
   Reg_s check;
   struct TBEntry *tbe;
   Reg prot;
   QCTable *qcTable;

   if (IS_PAL(P)) {
      if (P->alt_flag) {
         prot = ISP_DTLBPROT_ALT(P->ipr);
         qcTable = P->altDQC;
      } else {
         prot = 1<<KERNEL_MODE;
         qcTable = P->palDQC;
      }
   } else {
      prot = ISP_DTLBPROT(P->ipr);
      qcTable = P->curDQC;
   }
   

   /*
    * check va bits (should trap)
    */
   check = vA;
   if (check < 0) { 
      if ( (check&~VA_MASK)!=~VA_MASK) {
         CPUWarning("EV5_DTranslateVirtual: VA alignment failed vA=%lx check=%lx masked=%lx \n",
                    vA,check,check&~VA_MASK);
         if (trapNow) {
            if (isWrite) { 
               SetMM_Stat(P,(1<<MM_BVA)|(1<<MM_ACV)|(1<<MM_WR),vA);
            } else {
               SetMM_Stat(P,(1<<MM_BVA)|(1<<MM_ACV),vA);
            }
            EV5_Trap(P,TRAP_DTB_FAULT);
         }
         return MMU_EXCEPTION;
      }
   } else { 
      if ((vA & VA_MASK)!=vA) {
         CPUWarning("EV5_DTranslateVirtual: VA alignment failed vA=%lx masked=%lx \n",
                    vA,vA&VA_MASK);
         if (trapNow) {
            if (isWrite) { 
               SetMM_Stat(P,(1<<MM_BVA)|(1<<MM_ACV)|(1<<MM_WR),vA);
            } else {
               SetMM_Stat(P,(1<<MM_BVA)|(1<<MM_ACV),vA);
            }
            EV5_Trap(P,TRAP_DTB_FAULT);
         }
         return MMU_EXCEPTION;
      } 
   }
   
   vpfn = VADDR2TAG(vA);
	 
   if (((vA>>41)&3)==2 && ISP_DSP1ENABLED(P->ipr) ) {
      *pAddr = vA & PA_MASK;
      if ((P->alt_flag && ISP_SP1ACCESS_ALT(P->ipr)) ||
          (!P->alt_flag && ISP_SP1ACCESS(P->ipr))) {
         if ((vA & K1BASE)==K1BASE) {
            if ((int)vA == (int)alphaDebugParams.debugVATranslation) {
               CPUWarning("EV5_DTranslateVirtual: -UNCACHED- pc=%lx va=%lx pa=%lx\n",
                          P->PC, vA, *pAddr);
            }
            return MMU_UNCACHED;
         } else { 
            if (qcTable) QCInsert(qcTable,P->myNum,vpfn,*pAddr,1);
            if ((int)vA == (int)alphaDebugParams.debugVATranslation) {
               CPUWarning("EV5_DTranslateVirtual: -0- pc=%lx va=%lx pa=%lx\n",
                          P->PC, vA, *pAddr);
            }
            return MMU_SUCCESS;
         }
      } else {
         ASSERT( isWrite==0 || isWrite==1);
         if ((int)vA == (int)alphaDebugParams.debugVATranslation) {
            CPUWarning("EV5_DTranslateVirtual: -1- pc=%lx va=%lx pa=%lx\n",
                       P->PC, vA, *pAddr);
         }
         if (trapNow) {
            SetMM_Stat(P,(1<<MM_ACV) | (isWrite<<MM_WR),vA);
            EV5_Trap(P,TRAP_DTB_ACV);
         }
         return MMU_EXCEPTION;
      }
      
   }
   if (((vA>>30)&0x1fff)==0x1ffe &&  ISP_DSP0ENABLED(P->ipr)) {
      *pAddr = vA & BITMASK(30);
      if ((P->alt_flag && ISP_SP0ACCESS_ALT(P->ipr)) ||
          (!P->alt_flag && ISP_SP0ACCESS(P->ipr))) {
         if ((vA & K1BASE_32)==K1BASE_32) {
            return MMU_UNCACHED;
         } else {
            ASSERT(*pAddr < MEM_SIZE(0));

            if (qcTable) QCInsert(qcTable,P->myNum,vpfn,*pAddr,1);
            if ((int)vA == (int)alphaDebugParams.debugVATranslation) {
               CPUWarning("EV5_DTranslateVirtual: -2- pc=%lx va=%lx pa=%lx\n",
                          P->PC, vA, *pAddr);
            }
            return MMU_SUCCESS;
         }
      } else {
         ASSERT( isWrite==0 || isWrite==1);
         if ((int)vA == (int)alphaDebugParams.debugVATranslation) {
            CPUWarning("EV5_DTranslateVirtual: -3- pc=%lx va=%lx pa=%lx\n",
                       P->PC, vA, *pAddr);
         }
         if (trapNow) {
            SetMM_Stat(P,(1<<MM_ACV) | (isWrite<<MM_WR),vA);	 
            EV5_Trap(P,TRAP_DTB_ACV);
         }
         return MMU_EXCEPTION;
      }
   }
   
   tbe = TBLookup(P->tb,TB_DATA,VADDR2TAG(vA), ISP_CURRENT_DASN(P->ipr));
   if (tbe) { 
      Reg mask = tbe->pfn & ~BITMASK(tbe->gh*3);
      VA offset = vA & BITMASK(13+tbe->gh*3);
      *pAddr = PAGE2ADDR(mask) | offset;
      
      if ((*pAddr) >>(PA_BITS-1) !=0) {
         /* I/O stuff. fail */
         ASSERT(0);
      }
      if (!isWrite) {
         if (!(tbe->xre &prot)) {
            if ((int)vA == (int)alphaDebugParams.debugVATranslation) {
               CPUWarning("EV5_DTranslateVirtual: -4- pc=%lx va=%lx pa=%lx\n",
                          P->PC, vA, *pAddr);
            }
            if (trapNow) {
               if (tbe->ford) {
                  SetMM_Stat(P,(1<<MM_ACV)|(1<<MM_FOR),vA);
               } else {
                  SetMM_Stat(P,(1<<MM_ACV),vA);
               }
               EV5_Trap(P,TRAP_DTB_FAULT);
            }
            return MMU_EXCEPTION;
         }
         if (tbe->ford) {
            if ((int)vA == (int)alphaDebugParams.debugVATranslation) {
               CPUWarning("EV5_DTranslateVirtual: -5- pc=%lx va=%lx pa=%lx\n",
                          P->PC, vA, *pAddr);
            }
            if (trapNow) {
               SetMM_Stat(P,(1<<MM_FOR),vA);
               EV5_Trap(P,TRAP_DTB_FAULT);
            }
            return MMU_EXCEPTION;
         }
         if (qcTable) QCInsert(qcTable,P->myNum,vpfn,*pAddr,0);
         if ((int)vA == (int)alphaDebugParams.debugVATranslation) {
            CPUWarning("EV5_DTranslateVirtual: -6- pc=%lx va=%lx pa=%lx\n",
                       P->PC, vA, *pAddr);
         }
         return MMU_SUCCESS;
      } else {
         if (!(tbe->xwe & prot)) {
            if ((int)vA == (int)alphaDebugParams.debugVATranslation) {
               CPUWarning("EV5_DTranslateVirtual: -7- pc=%lx va=%lx pa=%lx\n",
                          P->PC, vA, *pAddr);
            }
            if (trapNow) {
               if (tbe->fow) {
                  SetMM_Stat(P,(1<<MM_ACV)|(1<<MM_FOW)|(1<<MM_WR),vA);
               } else {
                  SetMM_Stat(P,(1<<MM_ACV)|(1<<MM_WR),vA);
               }
               EV5_Trap(P,TRAP_DTB_FAULT);
            }
            return MMU_EXCEPTION;
         }
         if (tbe->fow) {
            if ((int)vA == (int)alphaDebugParams.debugVATranslation) {
               CPUWarning("EV5_DTranslateVirtual: -8- pc=%lx va=%lx pa=%lx\n",
                          P->PC, vA, *pAddr);
            }
            if (trapNow) {
               SetMM_Stat(P,(1<<MM_FOW)|(1<<MM_WR),vA);
               EV5_Trap(P,TRAP_DTB_FAULT);
            }
            return MMU_EXCEPTION;
         }
         if (qcTable) QCInsert(qcTable,P->myNum,vpfn,*pAddr,1);
         if ((int)vA == (int)alphaDebugParams.debugVATranslation) {
            CPUWarning("EV5_DTranslateVirtual: -9- pc=%lx va=%lx pa=%lx\n",
                       P->PC, vA, *pAddr);
         }
         return MMU_SUCCESS;
      }
   }
   if ((int)vA == (int)alphaDebugParams.debugVATranslation) {
      CPUWarning("EV5_DTranslateVirtual: -10- pc=%lx va=%lx pa=%lx\n",
                 P->PC, vA, *pAddr);
   }
   if (trapNow) {
      if (isWrite) {
         SetMM_Stat(P,(1<<MM_DMISS)|(1<<MM_WR),vA);
      } else {
         SetMM_Stat(P,(1<<MM_DMISS),vA);
      }
      EV5_Trap(P,TRAP_NDTB_MISS);
   }
   return MMU_EXCEPTION;
}



/*
 * XXX GAMMA and DELTA has different strategies to figure
 * XXX out the current instruction
 * XXX Should go as a callout.
 * XXX
 */
static void SetMM_Stat(AlphaState *P,Reg flags, VA vAddr)
{

   Inst ii = CPUVec.CurrentInstruction(P->myNum);
   union alpha_instruction inst= (union alpha_instruction)ii;

   if ((int)vAddr == (int)alphaDebugParams.debugVATranslation)
      CPUWarning("SetMM_Stat: cpu=%d flags=%lx vAddr=%lx lockedRegs=%lx\n",
                 P->myNum, flags, vAddr, P->trapState->lockedRegisters);
   ASSERT((flags & BITMASK(6))==flags);
   if (!(P->trapState->lockedRegisters&LOCKED_REGISTER_MMSTAT)) {
      P->trapState->atr[ATR_MM_STAT] = flags;
      P->trapState->atr[ATR_MM_STAT] |= (inst.m_format.opcode<<MM_OPC);
      P->trapState->atr[ATR_MM_STAT] |= (inst.m_format.ra<<MM_RA);
      P->trapState->lockedRegisters |= LOCKED_REGISTER_MMSTAT;
   } else {
      if (alphaDebugParams.debugTraps)
         CPUWarning("SetMM_Stat: IPR_MMSTAT is locked: lockedRegisters=%x\n",
                    P->trapState->lockedRegisters);
   }
   if (!(P->trapState->lockedRegisters&LOCKED_REGISTER_VA)) {
      P->trapState->atr[ATR_VA] = vAddr;
      P->trapState->lockedRegisters |= LOCKED_REGISTER_VA;
   } else {
      if (alphaDebugParams.debugTraps) 
         CPUWarning("SetMM_Stat: IPR_VA is locked: lockedRegisters=%x\n",
                    P->trapState->lockedRegisters);
   }
   if (!(P->trapState->lockedRegisters&LOCKED_REGISTER_VA_FORM)) {
      if (NT_MODE(P)) {
         P->trapState->atr[ATR_VA_FORM] = 
            (P->ipr[IPR_MVPTBR] & ~BITMASK(30)) |
            ( ((vAddr >>13)&BITMASK(19))<<3);
      }
      else {
         P->trapState->atr[ATR_VA_FORM] = 
            (P->ipr[IPR_MVPTBR] & ~BITMASK(33)) |
            ( ((vAddr >>13)&BITMASK(30))<<3);
      }
      P->trapState->lockedRegisters |= LOCKED_REGISTER_VA_FORM;
   } else {
      if (alphaDebugParams.debugTraps)
         CPUWarning("SetMM_Stat: IPR_VA_FORM is locked: lockedRegisters=%x\n",
                    P->trapState->lockedRegisters);
   }
}
   
static void SetIMM_Stat(AlphaState *P, Reg flags, VA vAddr)
{
   P->trapState->atr[ATR_IVA] = vAddr;
   P->trapState->atr[ATR_ITB_TAG] = vAddr;
   if (NT_MODE(P)) {
       P->trapState->atr[ATR_IVA_F] = (P->ipr[IPR_IVPTBR] & ~BITMASK(30)) |
          ( ((vAddr >>13)&BITMASK(19))<<3);
   }
   else {
       P->trapState->atr[ATR_IVA_F] = (P->ipr[IPR_IVPTBR] & ~BITMASK(33)) |
          ( ((vAddr >>13)&BITMASK(30))<<3);
   }
}

   


int EV5_ShadowRegistersUsed(AlphaState *P, VA PC)
{
   return (PC&0x1) && ISP_USE_SHADOW_REGISTERS(P->ipr[IPR_ICSR]);
}

void EV5_SwitchShadowRegisters(AlphaState *P, Reg newPC, Reg newICSR)
{
   int a,b,i;
   int newUse = (newPC&0x1) && ISP_USE_SHADOW_REGISTERS(newICSR);
#if 1 || defined(DEBUG)
   if (alphaDebugParams.debugTraps)
      CPUPrint("EV5_SwitchShadowRegisters newPC=%lx newUse=%d\n", newPC, newUse);
#endif
#if 0
   ASSERT( P->useShadowRegisters != newUse);
#endif
   if (newUse) {
      a = 0; b = 8;
   } else { 
      a = 8; b = 0;
   }
   for (i=8;i<=14;i++) {
      P->shadowRegs[i-8+a] = P->reg[i];
      P->reg[i] = P->shadowRegs[i-8+b];
   }
   P->shadowRegs[a+7] = P->reg[25];
   P->reg[25] = P->shadowRegs[b+7];
   P->useShadowRegisters = newUse;
}

/* ******************************************************************
 * Trap. Generate an exception 
 * ***************************************************************/
void EV5_Trap(AlphaState *P, int trap) 
{
   AlphaState *savedPE;
   ASSERT(trap);

   P->trapState->atr[ATR_EXC_ADDR] = P->PC;
   TRACE_ENTRY(TRACE_TRAP,P->myNum,P->PC);

   if ((trap&TRAP_PAL)==TRAP_PAL || trap==TRAP_ARITH) { 
      /*
       * skip instruction 
       */
      P->trapState->atr[ATR_EXC_ADDR] += 4;
   }
   if (trap == TRAP_ARITH) {
      Reg sum = P->trapState->atr[ATR_EXC_SUM];
      Reg mask = 0L;
      union alpha_instruction ainst = P->instr;
      if ((P->instr.word&0x8000) /* software completion bit */
          && (   (sum == 0)
                 || ((sum >> 9)&EXCSUM_SWC)))
         sum |= (EXCSUM_SWC << 9);
      else
         sum &= ~(long)(EXCSUM_SWC << 9);
      if (P->fpcr & FPCR_INV)
         sum |= (EXCSUM_INV << 9);
      if (P->fpcr & FPCR_DZE)
         sum |= (EXCSUM_DZE << 9);
      if (P->fpcr & FPCR_OVF)
         sum |= (EXCSUM_OVF << 9);
      if (P->fpcr & FPCR_UNF)
         sum |= (EXCSUM_UNF << 9);
      if (P->fpcr & FPCR_INE)
         sum |= (EXCSUM_INE << 9);
      if (P->fpcr & FPCR_IOV)
         sum |= (EXCSUM_IOV << 9);
      switch (ainst.common.opcode) {
      case op_opc14: /* fltm */
      case op_fltv:
      case op_flti:
      case op_fltl:
         mask = 1L << (ainst.f_format.fc + 32);
         break;
      case op_inta:
      case op_intl:
      case op_ints:
      case op_intm:
         mask = 1L << ainst.o_format.rc;
         break;
      }
      P->trapState->atr[ATR_EXC_SUM] = sum;
      P->trapState->atr[ATR_EXC_MASK] |= mask;
   }

   if (!IS_PAL(P) && 
       ISP_USE_SHADOW_REGISTERS(P->ipr[IPR_ICSR])) {
      EV5_SwitchShadowRegisters(P,P->ipr[IPR_PAL_BASE]+ trap, 
				P->ipr[IPR_ICSR]);
   }
   P->PC = P->ipr[IPR_PAL_BASE]+ trap;
   
   if (trap == TRAP_ARITH || alphaDebugParams.debugTraps)
      CPUWarning("@@@@ Trap: pc=%lx trap=%x exc_addr=%lx sum=%lx mask=%lx mmstat=%lx va=%lx va_form=%lx cycles=%ld\n",
                 P->PC, trap, P->trapState->atr[ATR_EXC_ADDR],
                 P->trapState->atr[ATR_EXC_SUM],
                 P->trapState->atr[ATR_EXC_MASK],
                 P->trapState->atr[ATR_MM_STAT], 
                 P->trapState->atr[ATR_VA],
                 P->trapState->atr[ATR_VA_FORM],
                 CPUVec.CycleCount(P->myNum));

   TRACE_ENTRY(TRACE_BB,P->myNum,P->PC);

   /*
    * Fail LL/SC
    */
   P->llAddr = -1;

   /*
    * Switch the curPE for the annotation!!!
    */
   savedPE = curPE;
   curPE = P;
   switch (trap) {
   case TRAP_RESET:
      EXC_EVENT(0);
      break;
   case TRAP_MCHK:
      EXC_EVENT(1);
      break;
   case TRAP_ARITH:
      EXC_EVENT(2);
      break;
   case TRAP_INTERRUPT:
      EXTERNAL_TRACE_INTERRUPT(P);
      EXC_EVENT(3);
      break;
   case TRAP_NDTB_MISS:
      EXC_EVENT(4);
      break;
   case TRAP_PDTB_MISS:
      EXC_EVENT(5);
      break;
   case TRAP_UNALIGN:
      EXC_EVENT(6);
      break;
   case TRAP_DTB_FAULT:
      EXC_EVENT(7);
      break;
   case TRAP_ITB_MISS:
      EXC_EVENT(8);
      break;
   case TRAP_ITB_ACV:
      EXC_EVENT(9);
      break;
   case TRAP_OPDEC:
      EXC_EVENT(10);
      break;
   case TRAP_FEN:
      EXC_EVENT(11);
      break;
   case TRAP_PAL:
      EXC_EVENT(12);
      break;
   default:
      if ((trap&TRAP_PAL) == TRAP_PAL) 
         EXC_EVENT(12);
   }
   ASSERT(P==curPE);
   curPE = savedPE;

   /* RFE_EVENT(); handled below */

   return ;
}

Reg EV5_MoveFromPriv(AlphaState *P,  int priv)
{
   Reg value;
   ASSERT(IS_PAL(P));
   switch (priv) {
   case IPR_PAL_R0:  case IPR_PAL_R1:  case IPR_PAL_R2: 
   case IPR_PAL_R3:  case IPR_PAL_R4:  case IPR_PAL_R5:
   case IPR_PAL_R6:  case IPR_PAL_R7:  case IPR_PAL_R8:
   case IPR_PAL_R9:  case IPR_PAL_R10: case IPR_PAL_R11:
   case IPR_PAL_R12: case IPR_PAL_R13: case IPR_PAL_R14:
   case IPR_PAL_R15: case IPR_PAL_R16: case IPR_PAL_R17:
   case IPR_PAL_R18: case IPR_PAL_R19: case IPR_PAL_R20:
   case IPR_PAL_R21: case IPR_PAL_R22: case IPR_PAL_R23:
   case IPR_PAL_R24: case IPR_PAL_R25: case IPR_PAL_R26:
   case IPR_PAL_R27: case IPR_PAL_R28: case IPR_PAL_R29:
   case IPR_PAL_R30: case IPR_PAL_R31:
   case IPR_PAL_BASE: 
   case IPR_IVPTBR:
   case IPR_DCMODE:
   case IPR_MAFMODE:
   case IPR_DPTE_TEMP:
      value = P->ipr[priv];
      break;

   case IPR_ISR:
      value = P->trapState->atr[ATR_ISR];
      break;
   case IPR_EXC_ADDR:
      value = P->trapState->atr[ATR_EXC_ADDR];
      break;

      /* the following are read/write unmodified */
   case IPR_PMCTR:  
   case IPR_ICERRSTAT:
   case IPR_DCERRSTAT:
   case IPR_MCSR:

      /* Interrup level registers and other registers that are ok */
   case IPR_ASTSR: 
   case IPR_ASTER: 
   case IPR_SIRR: 
   case IPR_ICSR:
   case IPR_PS: 
   case IPR_DTB_CM: 
      value = P->ipr[priv];
      break;

   case IPR_IPL:
      value = P->trapState->atr[ATR_IPL];
      break;
   case IPR_INTID:
      value = P->trapState->atr[ATR_INTID];
      break;

      /* 
       * Locked registers. Clear lock after SW read 
       */
   case IPR_VA:
      value = P->trapState->atr[ATR_VA];
      P->trapState->lockedRegisters= 0 ;
      break;
   case IPR_VA_FORM: 
      value = P->trapState->atr[ATR_VA_FORM];
      break;
   case IPR_MM_STAT:
      value = P->trapState->atr[ATR_MM_STAT];
      break;
   case IPR_IVA: 
      value = P->trapState->atr[ATR_IVA];
      break;
   case IPR_IVA_F: 
      value = P->trapState->atr[ATR_IVA_F];
      break;

   case IPR_EXC_MASK:
      value = P->trapState->atr[ATR_EXC_MASK];
      break;

   case IPR_EXC_SUM:
      value = P->trapState->atr[ATR_EXC_SUM];
      break;

      /* DTBL operations */
   case IPR_DTB_PTE:
   {
      struct TBEntry *tbe = TBIndex(P->tb,TB_DATA,P->dtbNLU);
      P->ipr[IPR_DPTE_TEMP] = tbe->reg;
      P->dtbNLU = (P->dtbNLU+1)%MAX_DTB;
      value = 0;
      break;
   }
      
   case IPR_CC_CTL:
   case IPR_CC: 
      CPUError("Cycle count read not implemented \n");
      /* same thing with a warning for those */
   case IPR_DCTESTCTL:
   case IPR_ITB_ASN:
   case IPR_DTB_ASN:
   case IPR_DCTESTTAG:
   case IPR_DCTESTTAGT:
      CPUWarning("PC=0x%lx hw_mfpr %s value=%lx: (treated as blank register) \n",P->PC,
		 GetIPRName(priv), P->ipr[priv]);
      value = P->ipr[priv];
      break;
      
      /* The following are read only no special case */

   case IPR_SL_RCV:
   case IPR_ICROWMAP:
   case IPR_DCFILLERR:
   case IPR_IPTE_TEMP:
      CPUWarning("PC=0x%lx hw_mfpr %s : (ronly treated as blank register) \n",P->PC,
		 GetIPRName(priv));
      value = P->ipr[priv];
      break;
      
      /* the following are write only */
   case IPR_HWINT_CLR:
   case IPR_SL_XMIT:
   case IPR_DC_FLUSH:
   case IPR_IC_FLUSH:
   case IPR_ALT_MODE:
   case IPR_DTBIA:
   case IPR_ITBIA:
      CPUError("PC=0x%lx hw_mfpr %x : wonly IPR read\n",P->PC,priv);
      value = 0;
      break;

      /* Now remain the heavy ones */
   case IPR_DTBIAP:
   case IPR_ITBIAP:
      CPUError("PC=%0x%lx hw_mfpr %x : nothing to read here \n",P->PC,priv);
      value = 0;
      break;
   default:
      CPUError("PC=0x%lx hw_mfpr 0x%x %s : not implemented \n",P->PC,priv,
	       GetIPRName(priv));
      value = 0;
      break;
   }
   if (alphaDebugParams.debugTraps)
      CPUWarning("EV5_MFPR: pc=%lx ipr=%x val=%lx\n",
                 P->PC, priv, value);
   return value;
}

void EV5_MoveToPriv(AlphaState *P, int priv, Reg newVal)
{
   Reg value = newVal;
   ASSERT(IS_PAL(P));
   switch (priv) {
   case IPR_PAL_R0:  case IPR_PAL_R1:  case IPR_PAL_R2: 
   case IPR_PAL_R3:  case IPR_PAL_R4:  case IPR_PAL_R5:
   case IPR_PAL_R6:  case IPR_PAL_R7:  case IPR_PAL_R8:
   case IPR_PAL_R9:  case IPR_PAL_R10: case IPR_PAL_R11:
   case IPR_PAL_R12: case IPR_PAL_R13: case IPR_PAL_R14:
   case IPR_PAL_R15: case IPR_PAL_R16: case IPR_PAL_R17:
   case IPR_PAL_R18: case IPR_PAL_R19: case IPR_PAL_R20:
   case IPR_PAL_R21: case IPR_PAL_R22: case IPR_PAL_R23:
   case IPR_PAL_R24: case IPR_PAL_R25: case IPR_PAL_R26:
   case IPR_PAL_R27: case IPR_PAL_R28: case IPR_PAL_R29:
   case IPR_PAL_R30: case IPR_PAL_R31:
   case IPR_PAL_BASE:
      break;
      /* the following are read/write unmodified */
   case IPR_PMCTR:  
   case IPR_ICERRSTAT:
   case IPR_DCERRSTAT:
   case IPR_CC_CTL:
   case IPR_CC: 
      break;

   case IPR_DTB_PTE:
      break; /* store it for now. wait for the tag */


      /* write masks of a few bits, read no sideeffect */
	
   case IPR_EXC_ADDR:
      value &= ~2;
      P->trapState->atr[ATR_EXC_ADDR] = value;
      break;
   case IPR_ASTSR:
   case IPR_ASTER:
      value &= 0xf;
      break;
   case IPR_IPL: 
      if (0 && (P->trapState->atr[ATR_IPL] > 25 || value > 25))
         CPUWarning("EV5_MTPR: pc=%lx exc_addr=%lx oldipl=%d newipl=%d\n",
                    P->PC, P->trapState->atr[ATR_EXC_ADDR], P->trapState->atr[ATR_IPL], value);

      value &= 0x1f;
      P->trapState->atr[ATR_IPL] = value;
      break;
   case IPR_PS: 
      value &= 3<<3;
      P->ipr[priv] = value;
      EXTERNAL_TRACE_PS(P);
      EV5_UpdateQCMode(P,TB_INSTR);
      break;
   case IPR_DTB_CM: 
      value &= 3<<3;
      P->ipr[priv] = value;
      EXTERNAL_TRACE_DTBCM(P);
      EV5_UpdateQCMode(P,TB_DATA);
      break;
   case IPR_ALT_MODE:
      value &= 3<<3;
      P->ipr[priv] = value;
      EV5_UpdateQCAltMode(P,TB_DATA);
      break;

   case IPR_MCSR:
      P->ipr[priv] = value;
      EXTERNAL_TRACE_MCSR(P);
      EV5_UpdateQCMode(P,TB_DATA);
      break;

   case IPR_SIRR: 
      value &= 0x7fff0;
      break;
      
   case IPR_ICSR: 
      value &= 0xffffff0300; 
      if (ISP_USE_SHADOW_REGISTERS(value) !=
	  ISP_USE_SHADOW_REGISTERS(P->ipr[IPR_ICSR])) {
	 EV5_SwitchShadowRegisters(P,P->PC,value);
      };
      P->ipr[priv] = value;
      EXTERNAL_TRACE_ICSR(P);
      EV5_UpdateQCMode(P,TB_INSTR);
      break;
   case IPR_IVPTBR:
   case IPR_MVPTBR:
      value &= 0xffffffffC0000000;
      break;
   case IPR_DCTESTCTL:
      value &= 0x1ffb;
      break;
   case IPR_DCMODE:
   case IPR_MAFMODE:
      value &= 0x3f;
      break;
   case IPR_ITB_ASN:
#if 0
      CPUWarning("Changing IPR_ITB_ASN at ra=0x%lx \n",P->reg[REG_RA]);
#endif
      value &= 0x7f0;
      if (value != P->ipr[priv]) { 
         TBNewASN(P->tb,TB_INSTR,ISP_CURRENT_IASN(P->ipr)); /* old value */
      }
      EXTERNAL_TRACE_ASN(P, value>>4);
      break;
   case IPR_DTB_ASN:
      value &= 0xFE00000000000000;
      if (value != P->ipr[priv]) { 
         TBNewASN(P->tb,TB_DATA,ISP_CURRENT_DASN(P->ipr)); /* old value */
      }
      EXTERNAL_TRACE_ASN(P, value>>57);
      break;
   case IPR_DCTESTTAG:
   case IPR_DCTESTTAGT:
      CPUWarning("PC=0x%lx hw_mtpr %x : (treated as blank register) \n",P->PC,priv);
      break;
      

   case IPR_EXC_SUM:
      value = 0;  /* automatically clear all bits */
      P->trapState->atr[ATR_EXC_SUM] = value;
      break;
   case IPR_EXC_MASK:
      value = 0;  /* automatically clear all bits */
      P->trapState->atr[ATR_EXC_MASK] = value;
      break;

      /* The following are read only no special case */

   case IPR_INTID:
   case IPR_SL_RCV:
   case IPR_ICROWMAP:
   case IPR_DCFILLERR:
   case IPR_MM_STAT: 
   case IPR_IPTE_TEMP:
   case IPR_DPTE_TEMP:
      CPUError("PC=0x%lx hw_mtpr %x : (ronly treated as blank register) \n",P->PC,priv);
      break;
      
      /* the following are write only */
   case IPR_HWINT_CLR:
   case IPR_SL_XMIT:
   case IPR_DC_FLUSH:
   case IPR_IC_FLUSH:
      break; 

   case IPR_DTBIA:
   {
      int i;
      for(i=0;i<MAX_DTB;i++) {
	 TBRemove(P->tb,TB_DATA,i);
      }
      break;
   }
   case IPR_DTBIS: 
   { 
      struct TBEntry *tbe = TBLookup(P->tb,TB_DATA,VADDR2TAG(value),
				     ISP_CURRENT_DASN(P->ipr));
      if (tbe) { 
	 TBRemove(P->tb,TB_DATA,tbe->index);
      }
      break;
   }
   case IPR_DTB_TAG:
      TBInsert(P->tb,TB_DATA,P->dtbNLU,P->ipr[IPR_DTB_PTE], 
	       VADDR2TAG(value),
	       ISP_CURRENT_DASN(P->ipr));
      P->dtbNLU = (P->dtbNLU+1)%MAX_DTB;
      break;
   case IPR_ITB_PTE:
      TBInsert(P->tb,TB_INSTR,P->itbNLU,value, 
	       VADDR2TAG(P->trapState->atr[ATR_ITB_TAG]),
	       ISP_CURRENT_IASN(P->ipr));
      P->itbNLU = (P->itbNLU+1)%MAX_ITB;
      break;

   case IPR_ITBIA:
   {
      int i;
      for(i=0;i<MAX_ITB;i++) {
	 TBRemove(P->tb,TB_INSTR,i);
      }
      break;
   }
   case IPR_ITBIS: 
   { 
      struct TBEntry *tbe =  TBLookup(P->tb,TB_INSTR,
                                      VADDR2TAG(value),
                                      ISP_CURRENT_IASN(P->ipr));
      if (tbe) {
	 TBRemove(P->tb,TB_INSTR,tbe->index) ;
      }
      break;
   }
   /* Now remain the heavy ones */
   case IPR_DTBIAP:
   {
      int i;
      for (i=0;i<MAX_DTB;i++) {
	 TBEntry *tbe = TBIndex(P->tb,TB_DATA,i);
	 if (!(tbe->asma&1)) {
	    TBRemove(P->tb,TB_DATA,i);
	 }
	 /* P->dtb[i].valid &= (P->dtb[i].asma&1); */
      }
      break;
   }

   case IPR_ITBIAP:
   {
      int i;
      for (i=0;i<MAX_ITB;i++) {
	 TBEntry *tbe = TBIndex(P->tb,TB_INSTR,i);
	 if (!(tbe->asma&1)) {
	    TBRemove(P->tb,TB_INSTR,i);
	 }	
	 /* P->itb[i].valid &= (P->itb[i].asma&1); */
      }
      break;
   }
   break;
   default:
      CPUError("PC=0x%lx hw_mtpr  %s : not implemented \n",P->PC,GetIPRName(priv));
      value = 0;
      break;
   }
   if (value != newVal) {
      CPUWarning("WARNING: PC=0x%lx hw_mtpr %s , value masked 0x%x -> 0x%x \n",
                 P->PC,GetIPRName(priv),newVal,value);
   }
   if (alphaDebugParams.debugTraps)
      CPUWarning("EV5_MTPR: pc=%lx ipr=%x val=%lx\n",
                 P->PC, priv, value);
   P->ipr[priv] = value;
}


void EV5_PALOpcode(AlphaState *P, Reg func)
{
   /* HRF 6-5 */
   VA pc = TRAP_PAL;

   int opdecFlow = 
      (func >= 0x40 && func <=0x7f) ||
      (func>0xBf) ||
      (func<0x3f && (CURRENT_MODE(P)!=KERNEL_MODE));

   if (func == 0x80) {
      /*
       * DEBUGGING BREAKPOINT. Do not increment the PC.
       *XXX ugly here, but hey. 
       */
      CPUWarning("EV5_PALOpcode: debugging breakpoint\n");
      GammaDebug(P->myNum,1);
      return;
   }


   if (!opdecFlow) {
      pc = pc | ((func &0x3f)<<6) | ((func&0x80)<<5);
#if defined(DEBUG_EV5)
      CPUWarning("%ld call_pal instruction func=%lx pc=0x%lx epc=0x%lx \n",
		 CPUVec.CycleCount(P->myNum),func,pc,P->PC);
#endif
   } else {
      pc = TRAP_OPDEC;
      CPUWarning("%ld call_pal instruction func=%lx pc=0x%lx epc=0x%lx \n",
		 CPUVec.CycleCount(P->myNum),func,pc,P->PC);
   }
   EV5_Trap(P,pc);
}


void EV5_HwRei(AlphaState *P) 
{
   ASSERT(IS_PAL(P));
   if (alphaDebugParams.debugTraps)
      CPUWarning("EV5_HwRei: pc=%lx ipr_exc_addr=%lx\n", P->PC, P->trapState->atr[ATR_EXC_ADDR]);
   P->PC = P->trapState->atr[ATR_EXC_ADDR];
   if (!IS_PAL(P) && ISP_USE_SHADOW_REGISTERS(P->ipr[IPR_ICSR])) {
      EV5_SwitchShadowRegisters(P,P->PC,P->ipr[IPR_ICSR]);
   }
   RFE_EVENT();
   if (P->takeInterruptAtRei)
      EV5_CheckForInterrupts(P, "EV5_HwRei");
}

MMUStatus EV5_HW_Store(AlphaState *P, uint32 i, Reg rbv, PA *pAddr, int *size)
{
   ev5_hwldst_format instr= ( ev5_hwldst_format)i;
   Reg vAddr = rbv + instr.hwmem_format.disp;

   *size = (instr.hwmem_format.quad?8:4);

   ASSERT(IS_PAL(P));
   ASSERT( instr.hwmem_format.opcode == PRIV_OP_HW_ST);
   if (instr.hwmem_format.phys) {
      *pAddr = (vAddr & PA_MASK);
      TRACE_ENTRY(TRACE_STORE_PHYS,P->myNum,vAddr);
   } else {
      MMUStatus status;
      if (instr.hwmem_format.alt) {
          P->alt_flag = 1;
      }
      status = EV5_DTranslateVirtual(P,vAddr,0,1,pAddr);
      P->alt_flag = 0;

      if (status==MMU_EXCEPTION) {
	 if (P->PC != P->ipr[IPR_PAL_BASE] + TRAP_NDTB_MISS) {
	    CPUError("HWSt: DTranslate failed with pc=0x%lx \n",
		     P->PC);
	 }
         ASSERT(instr.hwmem_format.vpte==0);
	 return MMU_EXCEPTION;
      } 
      if (status == MMU_UNCACHED) {
         CPUWarning("HW_Store virtual uncached at PC 0x%lx -> pAddr 0x%lx\n",
                    P->PC, *pAddr);
      }
      TRACE_ENTRY(TRACE_STORE,P->myNum,vAddr);
   }
   if (instr.hwmem_format.quad) {
      *pAddr &= ~7;
   } else {
      *pAddr &= ~3;
   }
   if (*pAddr>K1OFFSET) { 
      ASSERT(!instr.hwmem_format.lock_cond);
      return MMU_UNCACHED;
   } else if (instr.hwmem_format.lock_cond) {
      return MMU_SC;
   } else {
      return MMU_SUCCESS;
   }

   return 0;
}

MMUStatus EV5_HW_Load(AlphaState *P, uint32 i, Reg rbv, PA *pAddr, int *size)
{
   ev5_hwldst_format instr= ( ev5_hwldst_format)i;
   Reg vAddr = rbv + instr.hwmem_format.disp;

   *size = (instr.hwmem_format.quad?8:4);

   ASSERT(IS_PAL(P));
   ASSERT( instr.hwmem_format.opcode == PRIV_OP_HW_LD);
   if (instr.hwmem_format.phys) {
      *pAddr =(vAddr & PA_MASK);
      TRACE_ENTRY(TRACE_LOAD_PHYS,P->myNum,vAddr);
   } else {
      MMUStatus status;
      if (instr.hwmem_format.alt) {
          P->alt_flag = 1;
      }
      status = EV5_DTranslateVirtual(P,vAddr,0,1,pAddr);
      P->alt_flag = 0;

      /*###EJS question: this now does nothing.  Warning OK? */
      if (status==MMU_EXCEPTION) {
	 if ((P->PC == P->ipr[IPR_PAL_BASE] + TRAP_NDTB_MISS)
            &&(instr.hwmem_format.vpte)) {
            P->PC = P->ipr[IPR_PAL_BASE] + TRAP_PDTB_MISS;
         } else {
            CPUWarning("HW_Load pc 0x%lx != NDTB_MISS entry point or vpte not set.\n", P->PC);
         }
	
	 return MMU_EXCEPTION;
      } 
      if (status == MMU_UNCACHED) {
         CPUWarning("HW_Load virtual uncached at PC 0x%lx -> pAddr 0x%lx\n",
                    P->PC, *pAddr);
      }
      TRACE_ENTRY(TRACE_LOAD,P->myNum,vAddr);
   }
   if (instr.hwmem_format.quad) {
      if (*pAddr&0x7) {
#ifdef DEBUG_EV5 
	 CPUWarning("HW_Load at PC 0x%lx unaligned 0x%lx \n",
		    P->PC,*pAddr);
#endif
	 *pAddr = *pAddr & ~0x7;
      }
   } else {
      if (*pAddr&0x3) { 
#ifdef DEBUG_EV5
	 CPUWarning("HW_Load at PC 0x%lx unaligned 0x%lx \n",
		    P->PC,*pAddr);
#endif
	 *pAddr = *pAddr & ~0x3;
      }
   }
   if (*pAddr > K1OFFSET) {
      ASSERT(!instr.hwmem_format.lock_cond);
      return MMU_UNCACHED;
   } else if (instr.hwmem_format.lock_cond) {
      return MMU_LL;
   } else {
      return MMU_SUCCESS;
   }
}

void EV5_MiscReadClearSet(AlphaState *P, Reg *rap,int set)
{
   *rap = P->ipr[EVX$IPR_INTR_FLAG];
   if (set) {
      P->ipr[EVX$IPR_INTR_FLAG] = 1;
   } else {
      P->ipr[EVX$IPR_INTR_FLAG] = 0;
   }
}



/*
 * management of the QC tables.
 */

void EV5_UpdateQCMode(AlphaState *P, int type) 
{
   int mode;

   if (type==TB_INSTR) {
      mode = (P->ipr[IPR_PS] >>3)&3;
      if (!mode) {
         /* kernel */
         if (ISP_ISP0ENABLED(P->ipr)) mode++;
         if (ISP_ISP1ENABLED(P->ipr)) mode+=2;
      } else {
         mode += 3;
      }
      P->curIQC = TBNewMode(P->tb,type,mode);

   } else if (type==TB_DATA) {
      if (!P->palDQC) {
         P->palDQC = TBNewMode(P->tb,TB_DATA,ACCESS_PAL);
      }                               
      mode = (P->ipr[IPR_DTB_CM] >>3)&3;
      if (!mode) { 
         if (ISP_DSP0ENABLED(P->ipr)) mode++;
         if (ISP_DSP1ENABLED(P->ipr)) mode+=2;
      } else { 
         mode +=3;
      }
      P->curDQC = TBNewMode(P->tb,type,mode);
   } else {
      NOTREACHED();
      mode = 0;    
   }
   ASSERT( mode>=0 && mode < NUM_QC_MODES);
}

/* Set the QC table for when we are in ALT mode */

void EV5_UpdateQCAltMode(AlphaState *P, int type) 
{
   int mode;

   ASSERT(type==TB_DATA);

   mode = (P->ipr[IPR_ALT_MODE] >>3)&3;
   if (!mode) {
       if (ISP_DSP0ENABLED(P->ipr)) mode++;
       if (ISP_DSP1ENABLED(P->ipr)) mode+=2;
   } else {
       mode +=3;
   }
   P->altDQC = TBNewMode(P->tb,type,mode);
   ASSERT( mode>=0 && mode < NUM_QC_MODES);
}