nand.h
1.52 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
#ifndef __nand_h__
#define __nand_h__
#define NAND_OOB_SZ 16
#define NAND_PAGE_SZ 512
#define NAND_PAGE_SHIFT 9
#define NAND_SZ (64*1024*1024)
#define NAND_PAGES (NAND_SZ/NAND_PAGE_SZ)
#define NAND_PAGES_MASK (NAND_PAGES-1)
#define NAND_IMAGE_SZ (NAND_PAGES*(NAND_OOB_SZ+NAND_PAGE_SZ))
/* addressing only supports 8 bits of address within page */
#define NAND_ADDR_BLOCK_SHIFT 13
#define NAND_ADDR_PAGE_SHIFT 8
#define NAND_ADDR_PAGE_MASK ((1<<NAND_ADDR_PAGE_SHIFT)-1)
#define NAND_ADDR_OOB_MASK (NAND_OOB_SZ-1)
#define NAND_PAGE_PER_BLOCK (2<<(NAND_ADDR_BLOCK_SHIFT-NAND_PAGE_SHIFT))
#define NAND_BLOCKS (NAND_SZ/(NAND_PAGE_PER_BLOCK*NAND_PAGE_SZ))
#define NAND_CLE 0x1 /* command latch enable */
#define NAND_ALE 0x2 /* address latch enable */
#define NAND_MODE_CMD (NAND_CLE)
#define NAND_MODE_DATA (0)
#define NAND_MODE_ADDR (NAND_ALE)
#define NAND_CMD_READ_0 0x00
#define NAND_CMD_READ_1 0x01
#define NAND_CMD_PROGRAM 0x10
#define NAND_CMD_DUMMY_PROGRAM 0x11
#define NAND_CMD_READ_2 0x50
#define NAND_CMD_ERASE_0 0x60
#define NAND_CMD_ERASE_1 0xD0
#define NAND_CMD_STATUS 0x70
#define NAND_CMD_MP_STATUS 0x71
#define NAND_CMD_DATA_INPUT 0x80
#define NAND_CMD_READ_ID 0x90
#define NAND_CMD_RESET 0xff
#define NAND_STATUS_CMD_PASS 0x00
#define NAND_STATUS_CMD_FAIL 0x01
#define NAND_STATUS_READY 0x40
#define NAND_STATUS_BUSY 0x00
#define NAND_STATUS_WRITE_OK 0x80
#define NAND_STATUS_WRITE_NOK 0x00
void nand_init(void);
void nand_final(void);
void nand_ctrl(int w, unsigned char* v);
void nand_io(int w, unsigned char* v);
#endif