/*
 * Copyright (C) 1996-1998 by the Board of Trustees
 *    of Leland Stanford Junior University.
 * 
 * This file is part of the SimOS distribution. 
 * See LICENSE file for terms of the license. 
 *
 */

/* -*-mode:c-*- DO NOT MOVE THIS COMMENT */
/* $Id: flash_interface.c,v 1.1.1.1 2002/05/29 01:09:11 blythe Exp $ */

/*****************************************************************
 * flash_interface.c
 * 
 *****************************************************************/
#include <stdio.h>
#include <time.h>
#include <assert.h>
#include <stdlib.h>
#include "cpu_interface.h"
#include "mipsy.h"
#include "pcache.h"
#include "scache.h"
#include "memstat.h"
#include "memsys.h"
#include "eventcallback.h"
#include "cpu_interface.h"
#include "cpu_state.h"
#include "cp0.h"
#include "memory.h"
#include "string.h"
#include "simutil.h"
#include "tcl_init.h"
#include "registry.h"
#include "machine_defs.h"
#include "params.h"

#ifdef USE_FLASHLITE
#define ERROR FLASHLITE_ERROR
#define BIG_ENDIAN
#include "simosinterface.h"
#include "flash_interface.h"
#include "mipsy_interface.h" 
#include "datafind.h"


#ifdef SOLO
#include "solo.h"
#include "solo_page.h"
#else
#include "firewallhack.h"
#include "simmagic.h"
#include "firewall.h"
#endif

#endif

#ifdef HWBCOPY
#include "hw_bcopy.h"
#endif

/* for now just putting these here until there's a better place */
#define OSPC_LOADDR_SIMOS    (__MAGIC_OSPC_BASE + MAGIC_OSPC_LO_OFFS - K0BASE)
#define OSPC_HIADDR_SIMOS    (__MAGIC_OSPC_BASE + MAGIC_OSPC_HI_OFFS - K0BASE)
#define OSPC_VEC_REQ_ADDR_SIMOS    (__MAGIC_OSPC_BASE + MAGIC_OSPC_VEC_REQ_OFFS - K0BASE)
#define OSPC_VEC_REP_ADDR_SIMOS    (__MAGIC_OSPC_BASE + MAGIC_OSPC_VEC_REP_OFFS - K0BASE)

#define OSPC_RANGE_OFFSET(_offset_field_bits)  \
    ((0x1LL << (_offset_field_bits)) - 0x4000)

#define SWS_ZONENUM_BITS  4
#define SWS_ZONENUM_OFFSET  24
#define SWS_ZONE_FRAMALIAS   (0<<SWS_ZONENUM_OFFSET)
#define SWS_ZONE_FIREWALL    (3<<SWS_ZONENUM_OFFSET)
#define SWS_ZONE_FPROMALIAS (15<<SWS_ZONENUM_OFFSET)

#define SW_SERVICES_FLAVOR PI_UNC_FLAVOR_A
#define PIO_FLAVOR PI_UNC_FLAVOR_C

typedef enum {PIO_BYTE, PIO_HALF, PIO_WORD, PIO_DWORD} PIOAccessSize;
typedef enum {HIVE, FIRST_TOUCH, ROUND_ROBIN, HIVE_ROUND_ROBIN} AddrMapType;

#ifdef USE_FLASHLITE
static AddrMapType addrMap;

#ifndef SOLO
/* directMapLimit must be >= remap size AND must include any special
   addresses, which would normally include OSPC addrs, but they are handled
   separately because they need to be translated to non-coherent get space.
   Addresses that are less than directMapLimit don't go through Address Map conversion.*/
static int directMapLimit;
#define IS_DIRECT_MAP(addr) (((addr) & nodeOffsetMask) < directMapLimit)
#endif
#endif

/*
 * Struct to hold information about a pending memory request --
 * this is necessary because FlashAdvanceTime might change the state
 * of the cache, forcing the outgoing memory request to change.
 */
struct FlashPending {
   int active;
   int fcmd;
   int flavor;
   int cpuNum;
   PA addr;
} flashPending;
   
/*
 * Unlike the other memory systems we have, the flashlite memory system 
 * is currently a compile time option triggered by the USE_FLASHLITE
 * define. If this is not defined we provide stubs so simulator can
 * link without it. 
 */

#ifndef USE_FLASHLITE

/*****************************************************************
 * FlashliteInit
 *****************************************************************/
void 
FlashliteInit(void)
{
   { extern int LinkSymbolToRetrieveFlashFaultInit;
     LinkSymbolToRetrieveFlashFaultInit = 1;
   }

   CPUError("FlashliteCmd called when compile with !USE_FLASHLITE\n");
   return;
}

void 
FlashliteInstallTimer(int cpuNum, unsigned int interval, unsigned int timeLeft)
{
}

void 
FlashliteConfigDefaults(void)
{   
}

void
FlashliteRaiseSlot(int cpu, int slot)
{
   CPUError("FlashliteRaisedIBit called and USE_FLASHLITE not defined\n");
}
void
FlashliteClearSlot(int cpu, int slot)
{
   CPUError("FlashliteClearIBit called and USE_FLASHLITE not defined\n");
}

extern void 
InitMagicPromalias(char* addr, unsigned nbytes)
{
   CPUError("InitMagicPromalias called and USE_FLASHLITE not defined\n");
}

extern int
FlashliteWQFull(int cpu)
{
   return 0;
}
#else /* is defined(USE_FLASHLITE) */


/*
 * Since flashlite uses a thread model while SimOS uses a
 * calback back model we need to keep the two simulated clocks
 * in synch.  This is done by registering a callback when
 * the next thread wakeup will occur in flashlite. 
 */
static LL callbackTime = 0;           /* Time of next flashlite event to fire. */
static EventCallbackHdr callback;

extern bool mipsySyncWhenDone;

static void RunFlashlite(int cpuNum, EventCallbackHdr *hdr, void *v);
static Result FlashliteCmd(int cpuNum, int cmd, PA addr, int transId,
			   PA replacedPaddr, int writeback, byte *wbData);
static void FlashliteStatus(void);
static void FlashliteDone(void);
static void FlashliteDumpStats(void);
static void RetryUncachedOp(int cpuNum, EventCallbackHdr *hdr, void *arg);
static void ConvertNormalToCritWordFirst(LL *subBuffer, LL *alignedBuffer,
                              unsigned startAddr);
static void ConvertCritWordFirstToNormal(LL *subBuffer, LL *alignedBuffer,
                              unsigned startAddr);
static void GetUncachedAddr(int cpuNum, PA vAddr, unsigned long long *p_addr,
                            int *p_flavor);
static void SetConsistencyType(int cpuNum, enum ConsistencyType ctype);
static void FlashliteDrain(void);

#ifndef SOLO
static void DownloadProtocolState(void);
static void DownloadMiscbusState(void);
static void DMADone(int nodeNum, void *token, int status);
static void InitMagicPromalias(void);
extern void MipsyTakeBusError(int cpunum, int isIRef, LL addr);
static uint Uncached64To32Bit(unsigned long long addr64);
extern void MipsyErrUncachedOp(int cpuNum, uint addr);
extern void MipsyNakUncachedOp(int cpuNum);
#else
void
MipsyCacheError(int cpuNum, bool isAsync)
{
   CPUError("Wow!  How'd we get a MipsyCacheError with SoloMipsy?. (cpuNum %d, isAsync %u)\n", cpuNum, isAsync);
}
#endif

bool flashliteRunning = FALSE;

FILE *mipsy_cpulogF;
LL cpu_start_mem[SIM_MAXCPUS];
LL cpu_finish_mem[SIM_MAXCPUS];
LL *cpu_start = cpu_start_mem;
LL *cpu_finish = cpu_finish_mem;

static int bytesPerNode_shift;  /* supports backmap from FLASH
                                 * address to simos address in the 
                                 * hive layout
                                 */
static int nodeOffsetMask;


/*
 * State kept on behalf of a flashlite node. 
 */
static struct nodeState { 

   /*
    * In order to correctly handle uncached reads we maintain 
    * the state of outstanding uncached reads in the following
    * buffer. Note this assumes we have only one outstanding
    * uncached read per node. 
    */
   struct {
      bool    active;     /* State structure is inuse */
      PA      addr;       /* Address of uncached read */
      int     size;       /* Size of uncached read */
      bool    done;       /* Flashlite has returned data */
      int     status;     /* 0 if no error, data valid. */
      char    data[8];    /* Data if returned */
   } uncachedReadState;

   /*
    * Because of flow control problems we might have to stall an
    * uncached op. The following callback will unstall us
    * for a retry. 
    */
    EventCallbackHdr retryCallback;

   /*
    * Some stats for the node.
    */
   struct FlashStats {
      long long numGETs;
      long long numGETXs;
      long long numUPGRADEs;
      long long numWBs; 
      long long numNAKs;
   } stats;

} nodeState[SIM_MAXCPUS];

/*
 * In order to run SIMOS requires that all its addresses be remapped into
 * phyiscal addresses that are valid for flash.  The SOLO V_to_P already
 * handles this remapping for solo. 
 */
#ifndef SOLO

/*
 * Do the mappings between Simos and Flash addresses
 * This mapping currently assumes fewer than 128 CPUs 
 */
static signed char *simosPageToNode;
#define  SimosAddrToMemnum(_addr)     	\
               (simosPageToNode[(_addr)/FLASH_PAGE_SIZE])

static int nodeaddrMask;

static void InitSimosMemoryMap(void);
static unsigned int FlashAddrToSimosAddr(unsigned long long faddr);

#define FlashAddrFromAddr(_a,_b) FlashAddrFromSimosAddr((_a),(_b))
#define FlashAddrToAddr(_a) FlashAddrToSimosAddr((_a))
#endif

#ifdef SOLO
#define FlashAddrFromAddr(_a,_b) FlashAddrFromSoloAddr((_a),(_b))
#define FlashAddrToAddr(_a) FlashAddrToSoloAddr((_a))
#endif


unsigned FlashAddrCompress(unsigned long long flashAddr)
{
   return((unsigned)(FlashAddrToAddr(flashAddr)));
}


/*****************************************************************
 * MemsysInit
 *****************************************************************/
void 
FlashliteInit(void)
{

   int i;

   /*
    * You wouldn't get very far without upgrades or the wrong 
    * cache line size but the error messages generated by 
    * flashlite make it difficult to figure this out so we
    * explictly check here. 
    */
   if (NUM_MACHINES > 1) {
     CPUError("Flashlite won't run with multiple machines.\n");
   }
   if ((NUM_CPUS(0) == 1) && !UPGRADES_ON_UP) {
     CPUError("Flashlite won't run without upgrades.\n");
   }
   if (SCACHE_LINE_SIZE != (WORDS_IN_CACHELINE*8)) {
     CPUError("Flashlite requires SCacheLineSize of 128.\n");
   }
     
   memsysVec.type = FLASHLITE;
   memsysVec.NoMemoryDelay = 0;
   memsysVec.MemsysCmd = FlashliteCmd;
   memsysVec.MemsysDumpStats = FlashliteDumpStats;
   memsysVec.MemsysDone = FlashliteDone;
   memsysVec.MemsysStatus = FlashliteStatus;
   memsysVec.MemsysDrain = FlashliteDrain;

   bzero((char *)nodeState, sizeof(nodeState));

   callbackTime = 0;

   mipsy_cpulogF = cpulogF;

   FlashInitSim();
   flashliteRunning = TRUE;

   mipsySyncWhenDone = TRUE;

#ifndef SOLO
   InitMagicPromalias();

   /* run flash forward a bunch of cycles in order to get past its
    * protocol initialization.  This is important so we don't give it
    * cache misses while it is booting, plus it allows us to update
    * the firewall, NI registers, etc. from a checkpoint without
    * worrying about that state being smashed by protocol initialization.
    */
#ifdef notdef
   {
      int cycleoffset;
      ParamLookup(&cycleoffset, "MEMSYS.FLASH.FlashSimosCycleOffset", PARAM_INT);
        
      if (cycleoffset == 0) {
         CPUWarning("\rWARNING: No value specified for FlashSimosCycleOffset\n");
         CPUWarning("\rWARNING: Data restored from checkpoint may be overwritten by protocol boot\n");
      } else {
         CPUWarning("\rRunning flashlite forward by %d simos cycles to exec protocol boot\n",
                  cycleoffset);
         FlashSimosCycleOffset(cycleoffset);
         FlashAdvanceTime(0);
         CPUWarning("\rProtocol boot timeout complete, starting SimOS\n");
      }
   }
#endif
   {
      int cycleoffset;
      CPUWarning("\rRunning flashlite forward to exec protocol boot\n");

      cycleoffset = FlashAdvanceThroughMAGICBoot();
      FlashSimosCycleOffset(cycleoffset);
      CPUWarning("\rProtocol boot complete at cycle %d, starting SimOS\n", 
                 cycleoffset);
   }

   /* Initialize the address remap and fake firewall
    * support for flashlite.
    */
   /* Order is important -- JKB */
   DownloadMiscbusState();
   DownloadProtocolState();
   InitSimosMemoryMap();
   FlashFlushChangesToVerilogMem();
   for (i = 0; i < NUM_CPUS(0); i++) { 
      cpu_start[i] = MipsyReadTime(cpuNum);
   }
#endif
   { extern int LinkSymbolToRetrieveFlashFaultInit;
     LinkSymbolToRetrieveFlashFaultInit = 1;
   }
}

#ifndef SOLO
static void
DownloadMiscbusState(void)
{
  /* initialize workermask and workermatch for each cpu
   * This is a bit of a hack since the OS doesn't set these up
   * yet -- when we add that functionality we'll have mask/match
   * values in the checkpoint directly.
   *
   * xxx Also: set firewall shift. This is a hack, since we don't
   * checkpoint this value and the OS cannot be expected to set it
   * when resuming from a checkpoint. The firewall shift is the number
   * of positions the node number must be shifted right to get the cell
   * number, i.e. log2(CPUs/cell).
   */
  { 
     int cpuspercell, i;
     int numcells = NUM_CELLS(0);
     int wmask;
     
     if (numcells == 0) numcells = 1;

     cpuspercell = NUM_CPUS(0) / numcells;
     wmask = ~(cpuspercell - 1);

     for (i=0; i<NUM_CPUS(0); i++) {
        FlashSetWorker(i, wmask, i & wmask);

	FlashSetFWShift(i, GetLog2(cpuspercell));
     }
  }
}

void FlashliteInstallTimer(int cpuNum, unsigned int interval, unsigned int timeLeft)
{
   FlashInstallTimer(cpuNum, interval, timeLeft);
}

static void
DownloadProtocolState(void)
{
  int cpu, iec;

  /* XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
   *
   * NOTE:
   * More state needs to be downloaded here -- for now, we
   * only do the ibit table and the enable mask.
   *
   * XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
   */

  for (cpu = 0; cpu < NUM_CPUS(0); cpu++) {
    for (iec = 0; iec < 64; iec++) {
      FlashSetIbitTableEntry(cpu, iec, SimMagic_GetIbitTableEntry(cpu, iec));
    }
    FlashSetInterruptState(cpu,
			   SimMagic_GetIECPending(cpu),
			   SimMagic_GetIECTrans(cpu),
			   SimMagic_GetIECEnable(cpu));
  }
}

static void
DMADone(int nodeNum, void *token, int status)
{
   ASSERT(status == 0);
   CacheCmdDone(nodeNum, (int)token, 0,0,status, NULL);
}

unsigned long long
FlashAddrFromSimosAddr(unsigned int space, unsigned int addr)
{
   static int totalMemPerProc = 0;
   FLASHAddress faddr;
   faddr.ll = 0;

   if (totalMemPerProc == 0)
     ParamLookup(&totalMemPerProc, "MEMSYS.FLASH.TotalMemPerProc", PARAM_INT);

   if (IS_DIRECT_MAP(addr)) {
      faddr.fa.node = addr >> bytesPerNode_shift;
      faddr.fa.space = space;
      faddr.fa.offset = addr & nodeOffsetMask;
   } else {
      faddr.fa.node = SimosAddrToMemnum(addr);
      faddr.fa.space = space;

      switch (addrMap) {
      case FIRST_TOUCH:
      case ROUND_ROBIN:
         faddr.fa.offset = addr;
         break;

      case HIVE:
         faddr.fa.offset = addr & nodeOffsetMask;
         break;
      case HIVE_ROUND_ROBIN:
         faddr.fa.offset = addr & nodeOffsetMask;
         break;
      default:
         CPUError("AddrMap %d not supported.\n", addrMap);
      }
      ASSERT(faddr.fa.offset >= directMapLimit);
   }
/*   CPUPrint("FFS: %d, 0x%08x =>  0x%llx\n", space, addr, faddr.ll);*/
   ASSERT(faddr.fa.offset < totalMemPerProc);
   return faddr.ll;
}

static unsigned int
FlashAddrToSimosAddr(unsigned long long addr64)
{
   FLASHAddress faddr;
   uint addr;
   int flashNodeForSimNode0, simNode, ncpusPerCell, cell, cpu;

   faddr.ll = addr64;

   if (IS_DIRECT_MAP(faddr.fa.offset)) {
      addr = (faddr.fa.node << bytesPerNode_shift)
         | faddr.fa.offset;
   } else if (faddr.fa.offset >= OSPC_RANGE_OFFSET(OFFSET_FIELD_SIZE)) {
      /* ASSUME that there's nothing useful above OSPC_RANGE_OFFSET */
      addr = faddr.fa.offset - OSPC_RANGE_OFFSET(OFFSET_FIELD_SIZE) + OSPC_LOADDR_SIMOS;
   } else {
      switch (addrMap) {
      case FIRST_TOUCH:
      case ROUND_ROBIN:
         addr = faddr.fa.offset;
         break;
      case HIVE:
         addr = (faddr.fa.node << bytesPerNode_shift)
            | faddr.fa.offset;
         break;
      case HIVE_ROUND_ROBIN:
         ncpusPerCell = NUM_CPUS(0)/NUM_CELLS(0);
         cell = faddr.fa.node/ncpusPerCell;
         cpu = faddr.fa.node % ncpusPerCell;
         flashNodeForSimNode0 = (faddr.fa.offset/FLASH_PAGE_SIZE) % ncpusPerCell;
         simNode = cell * ncpusPerCell
            + (ncpusPerCell + cpu - flashNodeForSimNode0) % ncpusPerCell;
         addr = (simNode << bytesPerNode_shift)
            | faddr.fa.offset;
         break;
      default:
         CPUError("AddrMap %d not supported.\n", addrMap);
	 addr = 0; /* Get rid of compiler warning */
      }
   }
/*   CPUPrint("FTS: 0x%llx => 0x%08x\n", faddr, addr);*/
   ASSERT(addr < MEM_SIZE(0));
   return addr;
}
#endif


/*****************************************************************
 * FlashliteCmd
 *****************************************************************/
static Result
FlashliteCmd(int cpuNum, int cmd, PA addr, int transId,
             PA replacedPaddr, int writeback, byte *wbData)
             
{
   int fcmd,  flavor, len, way = 0;
   int former;
   int elimcmd, elimflavor;
   LL elimAddr, flashAddr;
   LL nextEvent;
   uint errorVec = 0;
   bool stall = TRUE;

#ifndef SOLO
   if (cmd & MEMSYS_DMAFLAVOR) {
      int isRead = ((cmd & MEMSYS_CMDMASK) == MEMSYS_GET);
      uint pciAddress;
      int node, deviceId, hit;
      FLASHAddress faddr;

      deviceId = TRANSID2DMACHANNEL(transId);
      ASSERT(deviceId < 4);
      if (simosPageToNode[addr/FLASH_PAGE_SIZE] < 0) {      
         simosPageToNode[addr/FLASH_PAGE_SIZE] = cpuNum;  /* First touch */
      }

      /*
       * Current we map flash address to node and office address and have
       * the DMA go through the PCI bus local to that node. We need to setup
       * the DMA mapping tables if we want to do this diffently.
       */
      faddr.ll = FlashAddrFromAddr(0,addr);
      node = faddr.fa.node; 
      pciAddress = 0x80000000 | faddr.fa.offset;

      /*
       * Push flashlite notion of time forward to that of the DMA. 
       */
      (void)  FlashAdvanceTime(MipsyReadTime(cpuNum));  

      hit = FlashDMAReq(node, deviceId, isRead, pciAddress, wbData, writeback, 
                        (void *)transId, DMADone);

      nextEvent = FlashAdvanceTime(MipsyReadTime(cpuNum));
      if (nextEvent != (LL)-1) {
         nextEvent += 1;
         if (callbackTime) {
            if (nextEvent < callbackTime) {
               EventCallbackUpdate(&callback, (SimTime) nextEvent);
               callbackTime = nextEvent;
            }
            
         } else {
            EventDoCallback(cpuNum,RunFlashlite, &callback, 0, 
                            nextEvent - MipsyReadTime(cpuNum));
            callbackTime = nextEvent;
         }
         
      }
      
      return (hit ? SUCCESS : STALL); 
   }    
#endif
   len = 0;
   switch (cmd & MEMSYS_CMDMASK) {
   case MEMSYS_GET:
      fcmd = PI_PROC_GET_REQ;
      if (cmd & MEMSYS_IFFLAVOR) {
	 flavor = PI_GET_INSTRUCTION;
      } else if (cmd & MEMSYS_LLFLAVOR) {
	 flavor = PI_GET_DATA_LL;
      } else {
         flavor = PI_GET_DATA;
         if (cmd & MEMSYS_PREFETCH) {
            flavor = PI_GET_DATA_PREFETCH;
         }
      }
      nodeState[cpuNum].stats.numGETs++;
      break;
   case MEMSYS_GETX:
      fcmd = PI_PROC_GETX_REQ;
      flavor = PI_GET_DATA;
      nodeState[cpuNum].stats.numGETXs++;
      if (cmd & MEMSYS_PREFETCH) {
         flavor = PI_GET_DATA_PREFETCH;
      }
      break;
   case MEMSYS_UPGRADE:
      fcmd = PI_PROC_UPGRADE_REQ;
      if (cmd & MEMSYS_SCFLAVOR) {
	 flavor = PI_UPGRADE_SC;
      } else if (cmd & MEMSYS_PREFETCH) {
         flavor = PI_UPGRADE_PREFETCH;
      } else {
	 flavor = PI_UPGRADE_NORMAL;
      }
      nodeState[cpuNum].stats.numUPGRADEs++;
      break;
      
   case MEMSYS_UNCWRITE:
      if (FlashUncachedWriteQueueFull(cpuNum)) {
         /* If flashlite can not accept this uncached write we
          * setup a callback to try again later. We will eventually
          * force the write into flashlite. 
          */
         if (!nodeState[cpuNum].retryCallback.active) { 
            EventDoCallback(cpuNum,RetryUncachedOp, &nodeState[cpuNum].retryCallback, (void *)0, 1);
         }
         return STALL;
      }
      stall = FALSE;
      fcmd = PI_PROC_UNC_WRITE_REQ;
      flavor = SW_SERVICES_FLAVOR;
      len = writeback;
      break;

   case MEMSYS_UNCWRITE_ACCELERATED:
      if (FlashUncachedWriteQueueFull(cpuNum)) {
         /* If flashlite can not accept this uncached write we
          * setup a callback to try again later. We will eventually
          * force the write into flashlite. 
          */
         if (!nodeState[cpuNum].retryCallback.active) { 
            EventDoCallback(cpuNum,RetryUncachedOp, &nodeState[cpuNum].retryCallback, (void *)0, 1);
         }
         return STALL;
      }
      stall = FALSE;
      fcmd = PI_PROC_UNC_PUT_SEQ_REQ;
				/* We don't actually know it's a _sequential_
				   accelerated, just that it's accelerated. */
      flavor = SW_SERVICES_FLAVOR;
      len = writeback;
      break;

   case MEMSYS_UNCREAD:
      if (!nodeState[cpuNum].uncachedReadState.active) {
         FlashBreakGatherIfNecessary(cpuNum);
	 /* DT:
	  * Old test was !FlashGloballyPerformed(cpuNum), WRONG! There
	  * was a window between the moment the fence count hits 0 and
	  * the moment the last entry is removed from the SMHT. We were
	  * falling off that window.
	  */
	 if (!EmptySMHT(cpuNum) || !FlashGloballyPerformed(cpuNum)) {
            if (!nodeState[cpuNum].retryCallback.active) { 
               EventDoCallback(cpuNum,RetryUncachedOp, &nodeState[cpuNum].retryCallback, (void *)1, 1);
            }
            return STALL;
         } 
         if (!FlashUncachedWriteQueueEmpty(cpuNum)) {
            if (!nodeState[cpuNum].retryCallback.active) { 
               EventDoCallback(cpuNum,RetryUncachedOp, &nodeState[cpuNum].retryCallback, (void *)1, 1);
            }
            return STALL;
         }
      }
      else {
         int size = writeback;
         if ((nodeState[cpuNum].uncachedReadState.addr == addr) &&
             (nodeState[cpuNum].uncachedReadState.size == size)) {
            if (nodeState[cpuNum].uncachedReadState.done) {
               /* An uncached read has finished. Return it to the caller. 
                */
               bcopy(nodeState[cpuNum].uncachedReadState.data, wbData, size);
               nodeState[cpuNum].uncachedReadState.active = FALSE;
               return SUCCESS;
            }
            else {
               /* Still outstanding. Wakeup must have been spurious. */
               return STALL;
            }
         }
         else {
            FlashBreakGatherIfNecessary(cpuNum);
	    /* NOTE (DT) see comment above */
            if (!EmptySMHT(cpuNum) || !FlashGloballyPerformed(cpuNum)) {
               if (!nodeState[cpuNum].retryCallback.active) { 
                  EventDoCallback(cpuNum,RetryUncachedOp, &nodeState[cpuNum].retryCallback, (void *)1, 1);
               }
               return STALL;
            } 
            if (!FlashUncachedWriteQueueEmpty(cpuNum)) {
               if (!nodeState[cpuNum].retryCallback.active) { 
                  EventDoCallback(cpuNum,RetryUncachedOp, &nodeState[cpuNum].retryCallback, (void *)1, 1);
               }
               return STALL;
            }
	    ASSERT(nodeState[cpuNum].uncachedReadState.done);
         }
      }

      /* A new request. Fill in buffer for tracking */
      nodeState[cpuNum].uncachedReadState.active = TRUE;
      nodeState[cpuNum].uncachedReadState.addr = addr;
      nodeState[cpuNum].uncachedReadState.size = writeback;
      nodeState[cpuNum].uncachedReadState.done = FALSE;
         
      fcmd = PI_PROC_UNC_READ_REQ;
      flavor = SW_SERVICES_FLAVOR;
      len = writeback;
      break;

   case MEMSYS_SYNC:
      /* An accelerated write may be in progress. If we want to
       * sync, then terminate the gather and let the write proceed.
       */
      FlashBreakGatherIfNecessary(cpuNum);
				/* SYNC is a special case that returns */
				/* without calling flashlite, just */
				/* querying its state */
      if (!FlashGloballyPerformed(cpuNum)) { 
         /* Must wait for flashlite */
         return STALL; 
      }
      return SUCCESS;
   default:
      assert(0);
      fcmd = 0;  
   }


   elimAddr = 0;    
   /* elimAddr.fa.space = 0;  -  For now only NORMAL address space */
   if (replacedPaddr == MEMSYS_NOADDR) {
      elimcmd = 0;  
      elimflavor = 0;
   } else {
#ifndef SOLO
      if ((replacedPaddr == OSPC_LOADDR_SIMOS) ||
          (replacedPaddr == OSPC_HIADDR_SIMOS) ||
          (replacedPaddr == OSPC_VEC_REQ_ADDR_SIMOS) ||
          (replacedPaddr == OSPC_VEC_REP_ADDR_SIMOS)) {
         FLASHAddress faddr;

         faddr.ll = 0;
         faddr.fa.node = cpuNum;
         faddr.fa.offset = OSPC_RANGE_OFFSET(OFFSET_FIELD_SIZE) 
            + (replacedPaddr - OSPC_LOADDR_SIMOS);
         elimAddr = faddr.ll;
      } else {         
         elimAddr = FlashAddrFromAddr(0,replacedPaddr);
      }
#else

#if 0
      /* JH: This is the safe, default version that doesn't provide the lock hack.
          In case the lock code crashes for you badly, this is a saving grace you can use*/
      elimAddr = FlashAddrFromAddr(0,replacedPaddr);
#else

      if ( ((replacedPaddr)&soloPACompressOffsetMask) >= soloBarrierBase) {
         /* barrier space overloading currently supported in SOLO only */

#ifdef DEBUG_PAGE_VERBOSE
	 CPUPrint("Barrier address detected, mapping to space 2 addr %x offset %x\n",
                  replacedPaddr, ((addr)&soloPACompressOffsetMask));
#endif /* DEBUG_PAGE_VERBOSE */
	 elimAddr = FlashAddrFromAddr(2,replacedPaddr);
	 elimAddr -= soloBarrierBase;
				/* This adjusts the phys addr so that
				   it begins from zero in space 2*/
      } else if (((replacedPaddr)&soloPACompressOffsetMask) >= soloLockBase) {
/* Lock space overloading currently supported in SOLO only */
#ifdef DEBUG_PAGE_VERBOSE
	 CPUPrint("Lock address (replace) detected, mapping to space 1 addr %x offset %x\n",
		  replacedPaddr, ((replacedPaddr)&soloPACompressOffsetMask));
#endif
	 elimAddr = FlashAddrFromAddr(1,replacedPaddr);
	 elimAddr -= soloLockBase;
				/* This adjusts the phys addr so that
				   it begins from zero in space 1*/
      } else {
	 elimAddr = FlashAddrFromAddr(0,replacedPaddr);
      }
#endif

#ifdef DEBUG_PAGE_VERBOSE
      CPUPrint("after decompression ELIM addr, pAddr = %llx\n",elimAddr);
#endif /* DEBUG_PAGE_VERBOSE */
#endif 
      if (writeback) {
	 elimcmd = PI_PROC_PUTX_REQ;
	 elimflavor = 0;
         nodeState[cpuNum].stats.numWBs++;
      } else {
	 elimcmd = PI_PROC_REPLACE_REQ;
	 elimflavor = PI_REPLACE_SHARED;
      }
      if (transId < 0) {
         stall = FALSE; /* Must be from a cache flush, don't stall the processor */
      }
   }

   /* Store request info in flashPending so that it can be checked
      while handling requests in FlashAdvanceTime */
   flashPending.active = 1;
   flashPending.fcmd = fcmd;
   flashPending.flavor = flavor;
   flashPending.cpuNum = cpuNum;
   flashPending.addr = (addr & ~(SCACHE_LINE_SIZE - 1));
   nextEvent = FlashAdvanceTime(MipsyReadTime(cpuNum));  
   /* Extract the fcmd/flavor from flashPending since it might have changed */
   flashPending.active = 0;
   fcmd = flashPending.fcmd;
   flavor = flashPending.flavor;

   if ((fcmd == PI_PROC_UNC_READ_REQ) 
       || (fcmd == PI_PROC_UNC_WRITE_REQ)
       || (fcmd == PI_PROC_UNC_PUT_SEQ_REQ)) {
      GetUncachedAddr(cpuNum, addr, &flashAddr, &flavor);
   } else {
#ifndef SOLO
      /*  Change fcmd to NC_GET for OSPC and map it to correct address */
      uint lineStartAddr = addr & ~(SCACHE_LINE_SIZE - 1);

      if ((lineStartAddr == OSPC_LOADDR_SIMOS) ||
          (lineStartAddr == OSPC_HIADDR_SIMOS) ||
          (lineStartAddr == OSPC_VEC_REQ_ADDR_SIMOS) ||
          (lineStartAddr == OSPC_VEC_REP_ADDR_SIMOS)) {
         FLASHAddress faddr;

         ASSERT(fcmd == PI_PROC_GET_REQ);
         fcmd = PI_PROC_NC_GET_REQ;

         faddr.ll = 0;
         faddr.fa.node = cpuNum;
         faddr.fa.offset = OSPC_RANGE_OFFSET(OFFSET_FIELD_SIZE) 
            + (addr - OSPC_LOADDR_SIMOS);
         flashAddr = faddr.ll;
      } else {
         if (simosPageToNode[addr/FLASH_PAGE_SIZE] < 0) {      
            simosPageToNode[addr/FLASH_PAGE_SIZE] = cpuNum;  /* First touch */
         }
         flashAddr = FlashAddrFromAddr(0,addr);
      }
#else

#if 0
      /* JH: This is the safe, default version that doesn't provide the lock hack.
          In case the lock code crashes for you badly, this is a saving grace you can use*/
      flashAddr = FlashAddrFromAddr(0,addr);
#else

      if ( ((addr)&soloPACompressOffsetMask) >= soloBarrierBase) {
         /* barrier space overloading currently supported in SOLO only */

#ifdef DEBUG_PAGE_VERBOSE
	 CPUPrint("Barrier address detected, mapping to space 2 addr %x offset %x\n",
                  addr, ((addr)&soloPACompressOffsetMask));
#endif /* DEBUG_PAGE_VERBOSE */
	 flashAddr = FlashAddrFromAddr(2,addr);
	 flashAddr -= soloBarrierBase;
				/* This adjusts the phys addr so that
				   it begins from zero in space 1*/
      } else if ( ((addr)&soloPACompressOffsetMask) >= soloLockBase) {
         /* lock space overloading currently supported in SOLO only */

#ifdef DEBUG_PAGE_VERBOSE
	 CPUPrint("Lock address detected, mapping to space 1 addr %x offset %x\n",addr, ((addr)&soloPACompressOffsetMask));
#endif /* DEBUG_PAGE_VERBOSE */
	 flashAddr = FlashAddrFromAddr(1,addr);
	 flashAddr -= soloLockBase;
				/* This adjusts the phys addr so that
				   it begins from zero in space 1*/
      } else {
	 flashAddr = FlashAddrFromAddr(0,addr);
      }
#endif
#ifdef DEBUG_PAGE_VERBOSE
      CPUPrint("after decompression cmd addr, pAddr = %llx\n",flashAddr);
#endif /* DEBUG_PAGE_VERBOSE */

#endif
   }

/*   CPUPrint("Mapping Mipsy: %8.8x to Flash: %16.16llx\n",
	      addr, flashAddr); */

   /* Grab way from the SMHT */
   if (transId >= 0) {
      way = SCACHE[GET_SCACHE_NUM(cpuNum)].SMHT[transId].scacheLRU;
   }

   former = SCACHE[GET_SCACHE_NUM(cpuNum)].SMHT[transId].formerState;
   nextEvent = FlashCmdToMagic(cpuNum, transId, 
			       FLASH_CMD_FORM(fcmd, flavor, way, len, former),
			       flashAddr, 
                               FLASH_CMD_FORM(elimcmd, elimflavor, way, 0, 0),
			       elimAddr, wbData, errorVec);


   assert(nextEvent >= MipsyReadTime(numNum));
   assert(nextEvent <= 0x7FFFFFFFFFFFFFFFLL);
   if (nextEvent != (LL)-1) {
      nextEvent += 1;
      if (callbackTime) {
	 if (nextEvent < callbackTime) {
	    EventCallbackUpdate(&callback, (SimTime) nextEvent);
	    callbackTime = nextEvent;
	 }

      } else {
	 EventDoCallback(cpuNum,RunFlashlite, &callback, 0, 
			 nextEvent - MipsyReadTime(cpuNum));
	 callbackTime = nextEvent;
      }

   }
   if (stall) {
      return STALL;
   } else {
      return SUCCESS;
   }
}

static void
RetryUncachedOp(int cpuNum, EventCallbackHdr *hdr, void *arg)
{
   int isRead = (int) arg;

   if (isRead) {
      /*
       * If writeQueue is still not empty try again later otherwise
       * we allow the processor to retry. 
       */
      if (!FlashUncachedWriteQueueEmpty(cpuNum)) {
         EventDoCallback(cpuNum,RetryUncachedOp, &nodeState[cpuNum].retryCallback, arg, 1);
         return;
      }
   } else { 
      /*
       * If writeQueue is still full try again later otherwise
       * we allow the processor to retry. 
       */
      if (FlashUncachedWriteQueueFull(cpuNum)) {
         EventDoCallback(cpuNum,RetryUncachedOp, &nodeState[cpuNum].retryCallback, arg, 1);
         return;
      }
   }
   MipsyReissueUncachedOp(cpuNum);
}


void
DumpCacheLine(char *data,int length)
{
   unsigned long *ld = (unsigned long *)data;
   int i;
   for (i=0; i< (length/sizeof(long)); i+=4) {
      CPUPrint("%8.8x %8.8x %8.8x %8.8x ",ld[i],ld[i+1], ld[i+2],ld[i+3]);
      if ((i+4)%8 == 0) {
	 CPUPrint("\n");
      }
   }

}

static void
RunFlashlite(int cpuNum, EventCallbackHdr *hdr, void *v)
{
   LL nextEvent;

   nextEvent = FlashAdvanceTime(MipsyReadTime(cpuNum));
   if (nextEvent == (LL)-1) {
      callbackTime = 0;
      return;
   }
   assert(nextEvent >= MipsyReadTime(cpuNum));
   assert(nextEvent <= 0x7FFFFFFFFFFFFFFFLL);
   callbackTime = nextEvent+1;
   EventDoCallback(cpuNum, RunFlashlite, &callback, 0, callbackTime - MipsyReadTime(0));
}


void
SimosCmdToSimos(int cpunum, int transId, int cmd, LL addr, int *cacheState,
                byte *data, uint errorVec)
{
   PA address;
   int wasDirty;
   LL lclData[WORDS_IN_CACHELINE];
   int remoteResult;	/* used to break stall into local vs. remote */
   FLASHAddress faddr;

   /* set REMOTE_HOME if this addr's is not local */
   faddr.ll = addr;
   remoteResult = (cpunum != faddr.fa.node) ? MEMSYS_RESULT_REMOTE_HOME : 0;

#ifndef SOLO
   if (cmd == PI_DP_UNC_READ_RPLY ||
       cmd == PI_DP_UNC_ERR_RPLY  ||
       cmd == PI_DP_UNC_NAK_RPLY)
     address = Uncached64To32Bit(addr);
   else {
#endif

#ifdef SOLO
     if (faddr.fa.space == 1) { /* Convert to lock range */
       faddr.fa.space = 0;
       faddr.fa.offset = faddr.fa.offset + soloLockBase;
				/* Offset to start of lock VA range */
       addr = faddr.ll;
#ifdef DEBUG_PAGE_VERBOSE
       CPUPrint("Lock address detected, mapping upwards for (FA) %16.16llx\n",
		addr);
#endif /* DEBUG_PAGE_VERBOSE */
     }

     if (faddr.fa.space == 2) { /* Convert to lock range */
       faddr.fa.space = 0;
       faddr.fa.offset = faddr.fa.offset + soloBarrierBase;
				/* Offset to start of lock VA range */
       addr = faddr.ll;
#ifdef DEBUG_PAGE_VERBOSE
       CPUPrint("Barrier address detected, mapping upwards for (FA) %16.16llx\n",
		addr);
#endif /* DEBUG_PAGE_VERBOSE */
     }

#endif /* SOLO */
     address = FlashAddrToAddr(addr);
#ifndef SOLO
   }
#endif

#ifdef DEBUG_PAGE_VERBOSE
   CPUPrint("After FAtoA: mipsy addr = %x\n",address);
#endif /* DEBUG_PAGE_VERBOSE */

/*   CPUPrint("Mapping Flash: %16.16llx to Mipsy: %8.8x\n",
	      addr, address); */

#ifndef SOLO
   if (errorVec && /* looks like an ECC... */
       /* ... but check whether this is an unc read -- only bit 0 matters */
       !(cmd == PI_DP_UNC_READ_RPLY && (errorVec & 0x1) == 0)) {
      if (cmd == PI_DP_UNC_READ_RPLY) {
         /* BUS ERROR the uncached ref */
         MipsyTakeBusError(cpunum, 0, address);
      } else {
         /* Asynchronous */
         MipsyCacheError(cpunum, 1); 
      }
      /*
	Transaction should be allowed to complete. At 3:30am we think it's
	safe to allow the CPU to continue.
      return;
      */
   } 
#endif

   switch (cmd) {
   case PI_DP_ERR_RPLY:
      /* bus error that goes through caches */
      CacheCmdDone(cpunum, transId, 0, MEMSYS_STATUS_ERROR, 
                   remoteResult | MEMSYS_RESULT_MEMORY, data);
      break;
   case PI_DP_NAK_RPLY:
      CacheCmdDone(cpunum, transId, 0, MEMSYS_STATUS_NAK, 
                   remoteResult | MEMSYS_RESULT_MEMORY, data);
      nodeState[cpunum].stats.numNAKs++;
#ifdef DEBUG
      CPUPrint("FLNAK: cpu %d count %lld\n", cpunum, 
                nodeState[cpunum].stats.numNAKs);
#endif
      break;
   case PI_DP_PUT_RPLY:
      if (data) { 
          ConvertCritWordFirstToNormal((LL *)data, lclData, 
                                       (unsigned)(addr & (SCACHE_LINE_SIZE-1)));
          data = (byte *)lclData;
      }
      CacheCmdDone(cpunum, transId, MEMSYS_SHARED, MEMSYS_STATUS_SUCCESS,
                   remoteResult | MEMSYS_RESULT_MEMORY, data);
      break;
   case PI_DP_PUTX_RPLY:
   case PI_DP_ACK_RPLY:
      if (data) { 
         ConvertCritWordFirstToNormal((LL *)data, lclData, 
                                       (unsigned)(addr & (SCACHE_LINE_SIZE-1)));
         data = (byte *)lclData;
      }
      CacheCmdDone(cpunum, transId, MEMSYS_EXCLUSIVE, MEMSYS_STATUS_SUCCESS,
                   remoteResult | MEMSYS_RESULT_MEMORY, data);
      break;

   case PI_DP_GET_REQ:
      if (CacheWriteback(cpunum, address, SCACHE_LINE_SIZE, (byte *)lclData)) {
	 *cacheState = DIRTYEX;
      } else {
	 *cacheState = SHARED;
      }
      ConvertNormalToCritWordFirst((LL*)data, lclData,
			      (unsigned)(address & (SCACHE_LINE_SIZE-1)));
      break;
   case PI_DP_UNC_NAK_RPLY:
      if (!nodeState[cpunum].uncachedReadState.active) {
         CPUError("PI_DP_UNC_NAK_RPLY without active uncached read\n");
      }
      nodeState[cpunum].uncachedReadState.active = FALSE;
#ifndef SOLO
      MipsyNakUncachedOp(cpunum);
#endif
      break;
   case PI_DP_UNC_ERR_RPLY:
      if (!nodeState[cpunum].uncachedReadState.active) {
         CPUError("PI_DP_UNC_ERR_RPLY without active uncached read\n");
      }
      /* xxx isIRef?  */
#ifndef SOLO
      MipsyErrUncachedOp(cpunum, nodeState[cpunum].uncachedReadState.addr);
#endif
      break;
   case PI_DP_UNC_READ_RPLY:
      if (!nodeState[cpunum].uncachedReadState.active) {
         CPUError("PI_DP_UNC_READ_RPLY without active uncached read\n");
      }
      bcopy(data, nodeState[cpunum].uncachedReadState.data, 
            nodeState[cpunum].uncachedReadState.size);

      nodeState[cpunum].uncachedReadState.done = TRUE;
      MipsyReissueUncachedOp(cpunum);
      break;
   case PI_DP_GETX_REQ:
      if (CacheExtract(cpunum, address, SCACHE_LINE_SIZE, &wasDirty, (char *)lclData)) {
	 if (wasDirty) 
	    *cacheState = DIRTYEX;
	 else
	    *cacheState = SHARED;
      } else {
	 *cacheState = INVAL;
      }
      ConvertNormalToCritWordFirst((LL *)data, lclData,
			      (unsigned)(address & (SCACHE_LINE_SIZE-1)));
      break;

   case PI_DP_INVAL_REQ:
      if (CacheInvalidate(cpunum, address, SCACHE_LINE_SIZE, 0, &wasDirty)) {
	 if (wasDirty) 
	    *cacheState = DIRTYEX;
	 else
	    *cacheState = SHARED;
      } else {
	 *cacheState = INVAL;
      }
      /* Check for a pending upgrade request to the same line,
         change it into a GETX if found. */
      if (flashPending.active && (flashPending.cpuNum == cpunum) && 
          (flashPending.addr == (address & ~(SCACHE_LINE_SIZE - 1))) &&
          (flashPending.fcmd == PI_PROC_UPGRADE_REQ)) {
         CPUPrint("MIPSY %lld: UPGRADE changing to GETX on cpu %d addr 0x%x\n",
                  (uint64)CPUVec.CycleCount(cpunum),cpunum,flashPending.addr);
         flashPending.fcmd = PI_PROC_GETX_REQ;
         if (flashPending.flavor == PI_UPGRADE_SC) {
            flashPending.flavor = PI_GET_DATA;
         }
      }
      break;

   default:
     printf("Unknown command from MAGIC 0x%x for address %#llx\n", cmd, faddr.ll);

   }
}


void
FlashliteStatus(void)
{
   FlashliteDumpStats();
}

#ifdef notdef
static char *
FlashliteStatus(int cpuNum)
{
   static struct FlashStats oldStats[SIM_MAXCPUS];
   static char buf[256];

   sprintf(buf, "%lld/%lld/%lld", 
           (nodeState[cpuNum].stats.numGETs - oldStats[cpuNum].numGETs) + 
               (nodeState[cpuNum].stats.numGETXs - oldStats[cpuNum].numGETXs),
           (nodeState[cpuNum].stats.numWBs - oldStats[cpuNum].numWBs),
           (nodeState[cpuNum].stats.numNAKs - oldStats[cpuNum].numNAKs));

   oldStats[cpuNum] = nodeState[cpuNum].stats;
   return buf;
}
#endif

static void 
FlashliteDone(void)
{
#ifndef SOLO
   int i;
   for (i = 0; i < NUM_CPUS(0); i++) { 
      cpu_finish[i] = MipsyReadTime(0);
   }
#endif
   FlashEnd();
}

#define FLASHLITE_DUMPEVERY -1
static void
FlashliteDumpStats(void)
{
   static int numCalls = 0;
   
   if(++numCalls == FLASHLITE_DUMPEVERY) {
      FlashDumpStats();
      numCalls = 0;
   }
}

void 
FlashliteResetStats(void)
{
    FlashResetStats();
}
void 
FlashliteStartCPU(int cpuNum)
{
  cpu_start[cpuNum] = MipsyReadTime(cpuNum);
}

void 
FlashliteStopCPU(int cpuNum)
{
   cpu_finish[cpuNum] = MipsyReadTime(cpuNum);
}


/*
 * The flash memory system deals with data in critical word first format
 * as we keep things in normal order. Here are two function for convert
 * data between the formats. 
 */
static void
ConvertNormalToCritWordFirst(LL *subBuffer,LL *alignedBuffer, unsigned startAddr)
{
   unsigned     offset;
   unsigned     count;
   unsigned     start;

   start = (startAddr & ((WORDS_IN_CACHELINE*8)-1)) >> 3;
 
   for (count=0; count < WORDS_IN_CACHELINE; count++) {
      offset = start ^ count;
      subBuffer[count] = alignedBuffer[offset];
   }
}
 
static void
ConvertCritWordFirstToNormal(LL *subBuffer, LL *alignedBuffer, unsigned startAddr)
{
   unsigned     offset;
   unsigned     count;
   unsigned     start;
 
   start = (startAddr & ((WORDS_IN_CACHELINE*8)-1)) >> 3;
 
   for (count=0; count < WORDS_IN_CACHELINE; count++) {
      offset = start ^ count;
      alignedBuffer[count] = subBuffer[offset];
   }
}
 

#ifndef SOLO

/* convert a 32 bit magic address to a full 64 bit addr.
   Also, return the zone */
static void
Uncached32To64Bit(int cpuNum, uint PA, unsigned long long *p_addr, int *p_flavor)
{
   FLASHAddress faddr;
   uint node, zone, zoneOffset;
   node = (PA >> __MAGIC_NODE_OFFS) & ((1 << __MAGIC_NODE_BITS) - 1);
   zone = (PA >> __MAGIC_ZONE_OFFS) & ((1 << __MAGIC_ZONE_BITS) - 1);
   zoneOffset = (PA & ((1 << __MAGIC_ZONE_OFFS) - 1));

   *p_flavor = SW_SERVICES_FLAVOR;
   faddr.ll = 0;
   faddr.fa.node = node;
   /* if the following assert is no longer true, we'll have to change the code
      below to use faddr.ll instead of faddr.fa.offset */
   ASSERT(OFFSET_FIELD_SIZE > (SWS_ZONENUM_BITS + SWS_ZONENUM_OFFSET));
   faddr.fa.offset = (((unsigned long long)zone) << SWS_ZONENUM_OFFSET)
      | zoneOffset;

   switch (zone) {
   case MAGIC_ZONE_BDOOR_DEV: {
      uint offset;
      *p_flavor = PIO_FLAVOR;
      /*
       * Since Flashlite doesn't support remote PIOs we always make the local.
       * Until we have remote device support we just pass the PA to thru Magic
       * back to SimosDispatchPIO().
       */
      offset = PA - __MAGIC_BASE;

      faddr.fa.node = cpuNum; /* Make PIOs always local. */
      faddr.fa.offset = offset;
      ASSERT(faddr.fa.offset == offset) /* Detects if fa.offset it too small */
      break;
      }
   case MAGIC_ZONE_FPROM_ALIAS:
      /* hack to convert 32bit frpom zone to 64bit fprom zone because they're not the same */
   {
#ifdef LARGE_SIMULATION
      if (node == 127) { /* 0xbfc0.... is node 127 */
#endif
         /* first, zero out bad zone number and part of offset fields */
         faddr.fa.offset &= ~(((1 << __MAGIC_ZONE_BITS) - 1) << SWS_ZONENUM_OFFSET);
         /* now add back the correct zone and portion of offset fields */
         faddr.fa.offset |= SWS_ZONE_FPROMALIAS | (MAGIC_ZONE_FPROM_ALIAS << __MAGIC_ZONE_OFFS);
#ifdef LARGE_SIMULATION
         /* need to add 'c' of 'bfc' back */
         faddr.fa.offset |= 0xc00000;
      }
#endif
   }
   break;
   case MAGIC_ZONE_FIREWALL:
      /* if firewall zone, need to fix it to match address mapping */
   {
      uint fwForAddr32 = faddr.fa.node << bytesPerNode_shift
         | (zoneOffset/sizeof(MagicRegister))*FLASH_PAGE_SIZE;
      FLASHAddress fwForAddr64;
      fwForAddr64.ll = FlashAddrFromSimosAddr(0, fwForAddr32);
      faddr.fa.node = fwForAddr64.fa.node;
      faddr.fa.offset = SWS_ZONE_FIREWALL
         | (fwForAddr64.fa.offset/FLASH_PAGE_SIZE)*sizeof(MagicRegister);
   }
   break;
   default:
      /* don't need to do anything */
      break;
   }
   *p_addr = faddr.ll;
}

static uint
Uncached64To32Bit(unsigned long long addr64)
{
   FLASHAddress faddr;
   uint addr32;
   int zone;

   faddr.ll = addr64;
   /* if the following assert is no longer true, we'll have to change the code
      below to use faddr.ll instead of faddr.fa.offset */
   ASSERT(OFFSET_FIELD_SIZE > (SWS_ZONENUM_BITS + SWS_ZONENUM_OFFSET));
   zone = faddr.fa.offset >> SWS_ZONENUM_OFFSET;
   if (zone == (SWS_ZONE_FPROMALIAS>>SWS_ZONENUM_OFFSET)) {
      zone = MAGIC_ZONE_FPROM_ALIAS;
   }

   addr32 = __MAGIC_BASE
      | (faddr.fa.node << __MAGIC_NODE_OFFS)
      | (zone << __MAGIC_ZONE_OFFS)
      | (faddr.ll & ((1 << __MAGIC_ZONE_OFFS) - 1));

   /*CPUPrint("U64T32 %llx => %x\n", addr64, addr32);*/
   return addr32;
}

void
GetUncachedAddr(int cpuNum, PA vAddr, unsigned long long *p_addr,
                int *p_flavor)
{
  FLASHAddress faddr;

  /*
   * For testing we convert all backdoor addresses to uncached 
   * ops to the IO space. 
   */
  faddr.ll = 0;

#ifdef HWBCOPY
  /* For now, if the given address is a valid physical address,
   * assume that we are doing an access to the MSG space.
   */
  if (vAddr < MEM_SIZE(0)) {
     if (simosPageToNode[vAddr/FLASH_PAGE_SIZE] < 0) {      
        simosPageToNode[vAddr/FLASH_PAGE_SIZE] = cpuNum; /* First touch */
     }
     *p_addr = FlashAddrFromSimosAddr(MSG,vAddr);
     CPUPrint("MSG: Message space write to 0x%08x (0x%016llx) on CPU %d\n",
              vAddr,*p_addr,cpuNum);
     return;
  }
#endif

  /* direct access firewall and PPC ver2 regions are translated specially
   * because they are not always local
   */

#ifdef OLD_INT
  if (vAddr >= PPC2_ZONES && vAddr < (PPC2_ZONES + PPC2_ZONES_SIZE)) {
     int szone = PPC2_ZONE(vAddr);

     faddr.fa.node = PPC2_NODE(vAddr);
     faddr.fa.space = NORMAL;
     *p_flavor = SW_SERVICES_FLAVOR;

     if (szone < PPCZONE_PPCCORE || szone >= PPCZONE_SWTLB) {
        /* each of these zones has a one-to-one translation of addresses
         * from the 1k of space offered by SimOS to the first 1k of
         * the 16 MB zone implemented by flashlite
         */
        LL mzone;
        switch (szone) {
        case PPCZONE_PPR:      mzone = SWS_ZONE_PPR;     break;
        case PPCZONE_DMAMAP:   mzone = SWS_ZONE_DMAMAP;  break;
        case PPCZONE_NODEMAP:  mzone = SWS_ZONE_NODEMAP; break;
        case PPCZONE_SWTLB:    mzone = SWS_ZONE_SWTLB;   break;
        default:
           CPUError("\rUncached access to unimplemented zone %d in flash_interface.c:GetUncachedAddr\n", szone);
           break;
        }
        faddr.fa.offset = mzone + PPC2_ZONE_OFFSET(vAddr);
     } else {
        /* ppcs are special because of the limited available address space in simos */
        int group = PPC2_PPCGROUP(szone);
        int op = PPC2_PPCOP(vAddr,szone);
        int seq = SWS_ZONE_PPC_SEQUENCE(vAddr);
        faddr.fa.offset = (SWS_ZONE_PPC 
                           + (group << SWS_ZONE_PPC_GROUP_OFFSET)
                           + (op << SWS_ZONE_PPC_OPCODE_OFFSET))
                           + seq;
     }
  } else if (vAddr>=SIMFW_DIRECT && vAddr<(SIMFW_DIRECT+SIMFW_DIRECT_SIZE)) {
     int pgnum = (vAddr - SIMFW_DIRECT) / sizeof(FWvector);
     int nodeoffset;

     /* get the full flash addr and mask off the high word (cpuNum) */
     nodeoffset = FlashAddrFromSimosAddr(0, pgnum*FLASH_PAGE_SIZE) & 0xffffffff;
     
     faddr.fa.node = simosPageToNode[pgnum];
     faddr.fa.offset = SWS_ZONE_FIREWALL
                        + (sizeof(FWvector)*(nodeoffset / FLASH_PAGE_SIZE));
     faddr.fa.space = NORMAL;
     *p_flavor = SW_SERVICES_FLAVOR;

  } else if (vAddr >= SIMRAMALIAS && vAddr < (SIMRAMALIAS + SIMRAMALIAS_SIZE)) {
     faddr.fa.node = 0;   /* node field ignored in an alias range */
     faddr.fa.offset = SWS_ZONE_FRAMALIAS + (vAddr - SIMRAMALIAS);
     faddr.fa.space = NORMAL;
     *p_flavor = SW_SERVICES_FLAVOR;
  } else if (vAddr >= SIMPROMALIAS 
             && vAddr < (SIMPROMALIAS + SIMPROMALIAS_SIZE)) {
     faddr.fa.node = 0;   /* node field ignored in an alias range */
     faddr.fa.offset = SWS_ZONE_FPROMALIAS + (vAddr - SIMPROMALIAS);
     faddr.fa.space = NORMAL;
     *p_flavor = SW_SERVICES_FLAVOR;
  } else if (vAddr >= PPC_RANGE && vAddr < (PPC_RANGE + PPC_RANGE_SIZE)) {
     faddr.fa.offset = 0x7480000 + (vAddr - PPC_RANGE);
     faddr.fa.space = IO;
     faddr.fa.node = cpuNum;
  } else if (vAddr >= SIMBASEADDR) { 
     faddr.fa.offset = (vAddr - SIMBASEADDR);
     faddr.fa.space = IO;
     faddr.fa.node = cpuNum; /* XXX - always local for now */
  } else {
     CPUWarning("Unknown uncached address 0x%x pasted to flashlite GetUncachedAddr cpu %d\n", 
                vAddr, cpuNum);
     faddr.fa.offset = vAddr;
     faddr.fa.node = cpuNum;
  }
#else

  Uncached32To64Bit(cpuNum, vAddr, &faddr.ll, p_flavor);
  
#endif

#ifdef notdef
  CPUWarning("GetUncachedAddr: input 0x%x output 0x%x%x (flavor 0x%x)\n",
             vAddr, ((int) (faddr.ll >> 32)), ((int) (faddr.ll & 0xffffffff)),
             *p_flavor);
#endif

#ifdef OLD_INT
  if ((faddr.ll & 0x7)
      && (vAddr >= PPC_RANGE) && (vAddr < PIO_RANGE)) {
     CPUWarning("GetUncachedAddr: unaligned PPC or PPR:  input 0x%x output 0x%x%x cpu %d\n",
                vAddr, 
                ((int) (faddr.ll >> 32)), 
                ((int) (faddr.ll & 0xffffffff)), cpuNum);
  }
#endif
  *p_addr = faddr.ll;
}

int
SimosDispatchPIO(int node_num, uint offset, int isRead, int size, volatile void *data)
{

   return SimMagic_DoPIO(node_num, offset + __MAGIC_BASE, isRead, size, (void *)data);
}

#ifndef SOLO
Bool
SimosGetMemoryAddr(LL p_addrll, Address *v_addr, int mem_type)
{
    *v_addr = (Address) PHYS_TO_MEMADDR(0,(PA)FlashAddrToSimosAddr(p_addrll));

   return TRUE;
}
#endif


/*
 * Interrupt hookup for flashlite.
 */
void
FlashliteRaiseSlot(int cpu, int slot)
{
   FlashRaiseInterrupt(cpu, slot);
}


void
FlashliteClearSlot(int cpu, int slot)
{
   FlashClearInterrupt(cpu, slot);
}

int  
SimosSetIntrBits(int cpunum, uint enableMask, uint intrBits)
{
#ifdef notdef
   /* hack so we can run SIPS through flashlite while all the
    * other interrupt support is still in SimOS
    */
   CPUWarning("SimosSetInterBits: Hack: assuming OSPC interrupt only\n");

   if (enableMask & (0x1)) {   /* OSPC LO */
      if (intrBits & (0x1)) {
         SimRaiseIBit(cpunum, IEC_OSPC_LO);
      } else {
         SimClearIBit(cpunum, IEC_OSPC_LO);
      }
   }

   if (enableMask & (0x1 << 1)) {  /* OSPC HI */
      if (intrBits & (0x1 << 1)) {
         SimRaiseIBit(cpunum, IEC_OSPC_HI);
      } else {
         SimClearIBit(cpunum, IEC_OSPC_HI);
      }
   }
   return 0;
#endif

   enableMask <<= 2; /* Skip over softeare interrupt bits */
   intrBits <<= 2;
   
   CPUVec.intrBits[cpunum] = (CPUVec.intrBits[cpunum] & ~enableMask) | intrBits;

   if (DEBUG_INTR()) {
     LogEntry("SSIB", cpunum, "emask: 0x%x  ibits: 0x%x  vec->ibits: 0x%x\n",
	      enableMask, intrBits, CPUVec.intrBits[cpunum]);
   }

   if (CPUVec.IntrBitsChanged) {
      (CPUVec.IntrBitsChanged)(cpunum);
   }

   return 0;
}

#endif

#ifdef SOLO
void
GetUncachedAddr(int cpuNum, PA vAddr, unsigned long long *p_addr, int *p_flavor)
{
    uint flavor;
 
    *p_addr = (unsigned long long) SoloV_to_P(cpuNum, vAddr, cpuNum, 0, &flavor);
    ASSERT(flavor == TLB_UNCACHED);
}

int
SimosDispatchPIO(int node_num, uint offset, int isRead, int size, volatile void *data)
{
   CPUError("SOLO got a PIO to the PCI bus!!!\n");
   return 0;
}

Bool
SimosGetMemoryAddr(LL p_addrll, Address *v_addr, int mem_type)
{
     (*v_addr) = (Address)SoloGetMemoryAddr(p_addrll);
     return ((*v_addr) ? TRUE : FALSE);
}   
int  
SimosSetIntrBits(int cpunum, uint enableMask, uint intrBits)
{
   CPUWarning("SOLO interrupt (%#x)\n",intrBits);
   return 0;

}
#endif /* SOLO */




/*
 * SetConsistencyType(int cpuNum, ConsistencyType ctype)
 * Set the write consistency model used by flashlite. 
 *
 * Note this routine does an uncached write to launch a PPC
 * to change the PI's opspace bits. This is intrusive (i.e. 
 * it cosumes time/resources to execute) and it assumes 
 * flashlite is in a state such that it can accept uncached
 * writes. 
 */

static void
SetConsistencyType(int cpuNum, enum ConsistencyType ctype)
{
#ifdef notdef
   LL faddr;
   Result ret;
   FlashCmd   cmd;
   LL data;
   LL nextEvent;


   ASSERT(flashliteRunning);

   if (FlashUncachedWriteQueueFull(cpuNum)) {
      CPUError("SetConsistencyType called with write queue full\n");
   }
 
   data = ((LL)ctype) << 62;
   cmd = FLASH_CMD_FORM(PI_PROC_UNC_WRITE_REQ,PI_UNC_FLAVOR_A,0,LEN_NODATA);
   faddr = (LL)PPC_ADDR(PPCG_MISC, PPCO_MISC_CONTEXTSWITCH);

   nextEvent = FlashCmdToMagic(cpuNum, 0, cmd, faddr, 0, 0, (char *)&data);
   if (nextEvent != (LL)-1) {
      nextEvent += 1;
      if (callbackTime) {
	 if (nextEvent < callbackTime) {
	    EventCallbackUpdate(&callback, (SimTime) nextEvent);
	    callbackTime = nextEvent;
	 }

      } else {
	 EventDoCallback(cpuNum,RunFlashlite, &callback, 0, 
			 nextEvent - MipsyReadTime(cpuNum));
	 callbackTime = nextEvent;
      }

   }
#endif
   CPUError("This is broken\n");

}


#ifndef SOLO
static void   FlashliteSetRemap(int cpunum, PA mask);
static void   FlashliteControlRemap(int cpunum, int isEnabled);
static unsigned int FlashliteGetNodeAddress(int cpunum);

static void FlashliteInitRemap(void);

static void
InitSimosMemoryMap(void)
{
   char *addrMapType;
   int i, memPerProc = 0;
   memsysVec.MemsysSetRemap = FlashliteSetRemap;
   memsysVec.MemsysControlRemap = FlashliteControlRemap;
   memsysVec.MemsysGetNodeAddress = FlashliteGetNodeAddress;

   FlashliteInitRemap();
   ParamLookup(&addrMapType, "MEMSYS.FLASH.FlashAddrMap", PARAM_STRING);
   if (addrMapType == NULL) 
      addrMapType = "ZeroOnly";
   simosPageToNode = (signed char *) calloc(1,MEM_SIZE(0)/FLASH_PAGE_SIZE);
   ParamLookup(&memPerProc, "MEMSYS.FLASH.TotalMemPerProc", PARAM_INT);
   bytesPerNode_shift = GetLog2(MEM_SIZE(0)/NUM_CPUS(0));
   ASSERT(MEM_SIZE(0) == ((1<<bytesPerNode_shift) * NUM_CPUS(0)));
   nodeOffsetMask = (1<<bytesPerNode_shift) - 1;

/* Hive currently uses only a single remap page, but using 2 pages just to be safe.
   There's an assert in remap code anyway... */
   directMapLimit = 2*FLASH_PAGE_SIZE;

   if (!strcmp(addrMapType, "FirstTouch")) {
      addrMap = FIRST_TOUCH;
      ASSERT(MEM_SIZE(0) <= memPerProc);

      for(i = 0; i < MEM_SIZE(0)/FLASH_PAGE_SIZE; i++) 
         simosPageToNode[i] = -1;
      CPUPrint("FlashAddrMap is FirstTouch\n");
   } else if (!strcmp(addrMapType, "RoundRobin")) {
      int pagesPerMem = 0, stripewidth = 0;

      addrMap = ROUND_ROBIN;
      ASSERT(MEM_SIZE(0) <= memPerProc);

      ParamLookup(&pagesPerMem, "MEMSYS.FLASH.RoundRobinStripe", PARAM_INT);
      ParamLookup(&stripewidth, "MEMSYS.FLASH.NumFlashNodes", PARAM_INT);
        
      if (stripewidth < 0) stripewidth = NUM_CPUS(0);
      for(i = 0; i < MEM_SIZE(0)/FLASH_PAGE_SIZE; i++) 
         simosPageToNode[i] = (i/pagesPerMem) % stripewidth;
      CPUPrint("FlashAddrMap is RoundRobin with stripe unit of %d\n",
               pagesPerMem);
   } else if (!strcmp(addrMapType, "HiveRoundRobin")) {
      int pageNum, cell, cpu, ncpusPerCell, pagesPerCPU;

      addrMap = HIVE_ROUND_ROBIN;

      /* compact roundrobin memory layout:
         pages are laid out across all cpus in cell using roundrobin allocation,
         and the offset is same as for Hive.
         */

      ncpusPerCell = NUM_CPUS(0)/NUM_CELLS(0);
      pagesPerCPU = MEM_SIZE(0)/NUM_CPUS(0)/FLASH_PAGE_SIZE;

      ASSERT(MEM_SIZE(0)/NUM_CPUS(0) <= memPerProc);

      CPUPrint("FlashAddrMap is HiveRoundRobin with ncells: %d\nncpusPerCell: %d\npagesPerCPU: 0x%x\nbytesPerNode_shift: %d   nodeOffsetMask: 0x%x   directMapLimit: 0x%x\n",
               NUM_CELLS(0), ncpusPerCell, pagesPerCPU,
               bytesPerNode_shift, nodeOffsetMask, directMapLimit);

      for (cell = 0; cell < NUM_CELLS(0); cell++) {
         for (cpu = 0; cpu < ncpusPerCell; cpu++) {
            int CPU = cell*ncpusPerCell + cpu;
            for (pageNum = pagesPerCPU*CPU; pageNum < pagesPerCPU*(CPU+1); pageNum++) {
               simosPageToNode[pageNum] = cell*ncpusPerCell + ((pageNum + cpu) % ncpusPerCell);
            }
         }
      }
   } else if (!strcmp(addrMapType, "Hive")) {
      int pageNum, numPages;
      addrMap = HIVE;
      ASSERT(MEM_SIZE(0)/NUM_CPUS(0) <= memPerProc);

      numPages = MEM_SIZE(0)/FLASH_PAGE_SIZE;
      for (pageNum = 0; pageNum < numPages; pageNum++) {
         PA paddr = pageNum*FLASH_PAGE_SIZE;
         int n;
         for (n = NUM_CPUS(0)-1; n >= 0; n--) {
            if (paddr >= remapVec->NodeAddr[n]) {
               simosPageToNode[pageNum] = n;
               break;
            }
         }
      }
      
      CPUPrint("FlashAddrMap is using the Hive mappings\n");
   } else {
      CPUPrint("FlashAddrMap is node zero only\n");
   }
#ifdef FIREWALL_HACK
   FlashliteDownloadFirewall();
#endif
}
/*****************************************************************
 * remap region support - XXX Once we get PPCs working this 
 * should use the remap support inside of flashlite. Until then
 * we fake it here. 
 *****************************************************************/


static void
FlashliteInitRemap(void)
{
   int i;

   /* We initialize backmapMask to all ones except for the
    * bits that might be set in the node id field
    */

   nodeaddrMask = ~0;
   for (i=0; i<NUM_CPUS(0); i++) {
      if (!remapVec->NodeAddrInitialized) {
	 remapVec->NodeAddr[i] = 
            MEMADDR_TO_PHYS(0, SIM_MEM_ADDR(0) + i * (MEM_SIZE(0) / NUM_CPUS(0)));
      }
      nodeaddrMask &= ~remapVec->NodeAddr[i];
   }
   remapVec->NodeAddrInitialized = 1;
}


static void
FlashliteSetRemap(int cpunum, PA mask)
{
   remapVec->RemapMask[cpunum] = mask;
}

static void
FlashliteControlRemap(int cpunum, int isEnabled)
{
   remapVec->RemapEnable[cpunum] = isEnabled;
   /* make sure directMapLimit is bigger than remap range */
   if (isEnabled)
      ASSERT(directMapLimit & remapVec->RemapMask[cpunum]);
}

static unsigned int 
FlashliteGetNodeAddress(int cpunum)
{
   return remapVec->NodeAddr[cpunum];
}

static void
InitMagicPromalias(void)
{
   int   cpu;
   char* pFram;  /* points into Flashlite's FRAM memory */
   char* pFprom; /* points into Flashlite's FPROM memory */
   char* fprom;  /* points to Simos's copy of the FPROM */

   fprom = sim_misc.fprom[0];
   if (fprom == NULL) return; /* none there */

   for (cpu= 0; cpu<NUM_CPUS(0); cpu++) {
      pFprom = FlashWritePromAlias(cpu, SWS_ZONE_FPROMALIAS,
				   fprom, FPROM_SIZE);
      /* For now, don't use SIMRAMALIAS_SIZE ... it's big! */
      pFram  = FlashWriteRamAlias(cpu, SWS_ZONE_FRAMALIAS,
				  sim_misc.fram[cpu], FRAM_SIZE);
      free(sim_misc.fram[cpu]);
      sim_misc.fram[cpu]  = pFram;
      sim_misc.fprom[cpu] = pFprom;
   }
   free(fprom);

   /* NOTE: at this point, the sim_misc fprom and fram pointers
    *       point directly into Flashlite memory. This allows a
    *       cohabitation between Flite and fast FRAM/FPROM access
    *       emulation through simmagic.
    */
}

/*
 * The following function is called by the memory fault command
 * (cpus/shared/faults.c) to set ECC for a number of lines, starting at a
 * specified address. The address MUST be KSEG0.
 */
int insertECC(unsigned int addr, int lines)
{
  LL faddr;
  int node;
  int cachelinesz = SCACHE_LINE_SIZE;

  if (!IS_KSEG0(addr) || lines <= 0 || !IS_KSEG0(addr+(unsigned)lines))
    return 1;

  faddr = FlashAddrFromAddr(0, MEMADDR_TO_PHYS(0, addr));
  node  = SimosAddrToMemnum(MEMADDR_TO_PHYS(0, addr));

  for ( ; lines > 0; lines--) {
    SetECC(node, faddr, ~0);
    addr += cachelinesz;
  }

  return 0;
}


#ifdef HWBCOPY
/******************************************************************
 * Hwbcopy annotations -- place pages on a specific node
 *****************************************************************/
static int HwbPlaceCmd(Tcl_Interp *interp, int argc, char *argv[]);

static tclcmd hwbcopyCmds[] = {
   "place",       4, HwbPlaceCmd,     " place address node",
   NULL,          0, NULL,            NULL
};

void HwbcopyAnnInit(Tcl_Interp *interp) 
{
   Tcl_CreateCommand(interp, "hwbcopy", DispatchCmd,
                     (ClientData) hwbcopyCmds, (Tcl_CmdDeleteProc*)NULL);

   Tcl_SetVar2(interp, "HWBCOPY", "hwbDMA", "No", TCL_GLOBAL_ONLY);
   Tcl_LinkVar(interp, "HWBCOPY(hwbDMA)",
               (char *) &hwbDMA, TCL_LINK_BOOLEAN);
   Tcl_SetVar2(interp, "HWBCOPY", "hwprefetch", "No", TCL_GLOBAL_ONLY);
   Tcl_LinkVar(interp, "HWBCOPY(hwprefetch)",
               (char *) &hwprefetch, TCL_LINK_BOOLEAN);
   Tcl_SetVar2(interp, "HWBCOPY", "hwprefRange", "0", TCL_GLOBAL_ONLY);
   Tcl_LinkVar(interp, "HWBCOPY(hwprefRange)",
               (char *) &hwprefRange, TCL_LINK_INT);
   Tcl_SetVar2(interp, "HWBCOPY", "hwprefDepth", "0", TCL_GLOBAL_ONLY);
   Tcl_LinkVar(interp, "HWBCOPY(hwprefDepth)",
               (char *) &hwprefDepth, TCL_LINK_INT);
   Tcl_SetVar2(interp, "HWBCOPY", "hwbDMAChannels", "1", TCL_GLOBAL_ONLY);
   Tcl_LinkVar(interp, "HWBCOPY(hwbDMAChannels)",
               (char *) &hwbDMAChannels, TCL_LINK_INT);
   Tcl_SetVar2(interp, "HWBCOPY", "hwbDMADelay", "0", TCL_GLOBAL_ONLY);
   Tcl_LinkVar(interp, "HWBCOPY(hwbDMADelay)",
               (char *) &hwbDMADelay, TCL_LINK_INT);

}

static int HwbPlaceCmd(Tcl_Interp *interp, int argc, char *argv[])
{
   int node;
   int pAddr;
   int page;
   char *addrMapType;

   ParamLookup(&addrMapType, "MEMSYS.FLASH.FlashAddrMap", PARAM_STRING);

   if ((memsysVec.type == FLASHLITE) && (!strcmp(addrMapType, "FirstTouch"))) {
      if (argc < 4) {
         Tcl_AppendResult(interp, "not enough arguments to hwbcopy place", NULL);
         return TCL_ERROR;
      }
      
      Tcl_GetInt(interp, argv[3], &node);
      Tcl_GetInt(interp, argv[2], &pAddr);
      page = pAddr / FLASH_PAGE_SIZE;
      
      if (simosPageToNode[page] == -1) {
         simosPageToNode[page] = node;
         /*      CPUWarning("Page 0x%x being placed on node %d\n",pAddr,node);*/
      } else if (node != simosPageToNode[page]) {
         CPUWarning("Tried to place page 0x%x on node %d, already on node %d\n",pAddr,node,simosPageToNode[page]);
      }
   }
   return TCL_OK;
}
#endif /* HWBCOPY */
#endif



#ifndef SOLO
void FlashliteUndirtify(int leaveShared)
{
   /* first drain memory system, then undirtify */
   FlashDrainMemSys();
   FlashUndirtify(leaveShared);
}

void SyncMemory(void)
{
   datafindHeader *dfH;
   int pAddr;
   int nDirty = 0, nCrit = 0;

   FlashFreezeMemSys();
   for (pAddr = 0; pAddr < MEM_SIZE(0); pAddr += SCACHE_LINE_SIZE) {
      dfH = FlashGetAppData(FlashAddrFromAddr(0, pAddr));

      ASSERT(dfH->numCopies > 0);
      if (dfH->dirty) {
#ifdef SOLO
         LL *memAddr = (LL *)pAddr;
#else
         LL *memAddr = (LL *)PHYS_TO_MEMADDR(0, pAddr);
#endif

         ASSERT(dfH->numCopies == 1);

         if (dfH->critWordOffset[0]) {
            ConvertCritWordFirstToNormal((LL*)(dfH->dataCopies[0]), 
                                         memAddr, dfH->critWordOffset[0]);
            nCrit++;
         } else {
            bcopy(dfH->dataCopies[0], memAddr, SCACHE_LINE_SIZE);
         }
         nDirty++;	/* just for stats */
      } else {
         /* clean:  so there must be a copy in memory, and I don't need to do anything */
         ASSERT((dfH->dataLocation[dfH->numCopies-1] & DATAFIND_LOCATION_TYPE_MASK) == DATAFIND_LOCATION_MEMORY);
      }
   }

   FlashUnfreezeMemSys();
   CPUWarning("%d critical-word ordered lines, %d dirty lines, %d total lines\n", nCrit, nDirty, MEM_SIZE(0)/SCACHE_LINE_SIZE);
}
#endif


/*
  Routines for reading from / writing to the FPROM and FRAM.
  Check for the [vAddr, vAddr+nbytes) to see if it's in FPROM/FRAM range.
  If so, copy the data into buf and return 1 to indicate data was found
  in FPROM/FRAM.
 */

int
GetFPROMAndFRAM(int cpunum, VA vAddr, uint nbytes, char *buf)
{
#ifndef SOLO
   if (vAddr >= FRAM_BASE && vAddr+nbytes < FRAM_BASE + FRAM_SIZE) {
      unsigned raddr = vAddr - FRAM_BASE + SWS_ZONE_FRAMALIAS;
      
      FlashReadRamAlias(cpunum, buf, (unsigned long long)raddr, nbytes);
      return 1;
   }
   
   if (vAddr >= FPROM_BASE && vAddr+nbytes < FPROM_BASE + FPROM_SIZE) {
      unsigned raddr = vAddr - FPROM_BASE + SWS_ZONE_FPROMALIAS;
      
      FlashReadPromAlias(cpunum, buf, (unsigned long long) raddr, nbytes);
      return 1;
   }
#endif
   return 0;
}

int
PutFPROMAndFRAM(int cpunum, VA vAddr, uint nbytes, char *buf)
{
#ifndef SOLO
   if (vAddr >= FRAM_BASE && vAddr+nbytes < FRAM_BASE + FRAM_SIZE) {
      unsigned raddr = vAddr - FRAM_BASE + SWS_ZONE_FRAMALIAS;
      
      FlashWriteRamAlias(cpunum, (unsigned long long)raddr, buf, nbytes);
      return 1;
   }
   
   if (vAddr >= FPROM_BASE && vAddr+nbytes < FPROM_BASE + FPROM_SIZE) {
      unsigned raddr = vAddr - FPROM_BASE + SWS_ZONE_FPROMALIAS;
      
      FlashWritePromAlias(cpunum, (unsigned long long) raddr, buf, nbytes);
      return 1;
   }
#endif
   return 0;
}


void
FlashliteDrain(void)
{
#ifndef SOLO
   uint cpu, i, numBadNodes, *badNodes;
   FlashDrainMemSys();

   /* download nodemap */
   numBadNodes = FlashGetBadNodesList(0, &badNodes);
   for (i = 0; i < numBadNodes; i++) {
      int badNode = badNodes[i];

      /* NOTE:  this is not exactly what flashlite does for non-Hive addr maps
         due to roundrobin effect */
      uint memPerCPU = MEM_SIZE(0)/NUM_CPUS(0);
      uint startAddr = memPerCPU * badNode;
      uint endAddr = memPerCPU * (badNode+1);
      uint addr;

      for (addr = startAddr; addr < endAddr; addr += SCACHE_LINE_SIZE) {
         SimMagic_MakeIncoherent(addr);
      }
      CPUVec.ResetCPU(badNode);
      ResetCPUs(badNode, badNode);
   }

   /* incoherent lines on working nodes */
   for (cpu = 0; cpu < NUM_CPUS(0); cpu++) {
      uint *badLines;
      uint numBadLines;
      FLASHAddress faddr;

      /* skip bad nodes */
      for (i = 0; i < numBadNodes; i++) {
         if (cpu == badNodes[i])
            break;
      }
      if (i != numBadNodes)
         continue;

      faddr.ll = 0;
      faddr.fa.node = cpu;
      numBadLines = FlashGetIncoherentLinesList(cpu, &badLines);
      for (i = 0; i < numBadLines; i++) {
         faddr.fa.offset = badLines[i];
         SimMagic_MakeIncoherent(FlashAddrToSimosAddr(faddr.ll));
      }
      free(badLines);
      if (numBadLines) CPUWarning("WARNING: incoherent lines found.\n");
   }
   free(badNodes);

   /* download firewall */
   if (SIMFIREWALL_ON) {
      FLASHAddress faddr;
      LL prot;
      uint p;

      for (p = 0; p < MEM_SIZE(0); p += FLASH_PAGE_SIZE) {
         faddr.ll = FlashAddrFromSimosAddr(0,p);
         prot = FlashGetAccessControlVector(faddr.ll);
         sim_firewall_set_page_prot_raw(faddr.fa.node,
                                        faddr.fa.offset/FLASH_PAGE_SIZE,
                                        prot);
      }
   }

   /* SIPS */
   for (cpu = 0; cpu < NUM_CPUS(0); cpu++) {
      int numOSPC;
      char *queue = NULL;

      numOSPC = FlashGetOSPCHiQueue(cpu, (LL **)&queue);
      for (i = 0; i < numOSPC; i++) {
         CPUWarning("OSPCHi in flight\n");
         SimMagic_InsertOspcHiQueue(cpu, queue + i*SCACHE_LINE_SIZE);
      }
      if (queue)
         free(queue);

      numOSPC = FlashGetOSPCLoQueue(cpu, (LL **)&queue);
      for (i = 0; i < numOSPC; i++) {
         CPUWarning("OSPCLo in flight\n");
         SimMagic_InsertOspcLoQueue(cpu, queue + i*SCACHE_LINE_SIZE);
      }
      if (queue)
         free(queue);
   }
   /* remove flashlite clock advance callback */
   EventCallbackRemove(&callback);

#endif
}

extern int
FlashliteWQFull(int cpu)
{
   if ((memsysVec.type == FLASHLITE) && FlashWriteQueueFull(cpu)) { 
      return 1;
   } else {
      return 0;
   }
}

#endif /* is defined(USE_FLASHLITE) */