//
//   T a b u l a r    F i l e    F o r m a t
//

The tabular file format is designed for ease of generation by
formatted dump code in the C simulation and Verilog simulation.
Various 'converters' are available for creating Verilog or Qsim
test fixtures and for creating timing diagrams from tabular files.

The basic format is:
	#  comments
	Signal definiton 0
	Signal definiton 1
            .
            .
            .
	Signal definiton n-1
	BLANK LINE
	Vector 0
	Vector 1
            .
            .
            .
	Vector m-1
 	EOF

These Signal Definition and Vector parts *must* be separated by a blank line. This
should be the only blank line in the file.  You can use the comment character '#'
to add space between lines. 

The Signal definiton section should also be at the top of the file followed
by the vectors.  Everything on a line after a '#' character is ignored. Lines
may be 'wrapped' to the next line by placing a '\' character at the end of the 
line.  


//
//  Signal Definitions
//

In the follwong definitions, fields in between brackets '< >' are user supplied 
names or values.

For multi-bit signals (buses) the format is:
	<bus_name>[<msb>:<lsb>] <type> <options>

For single bit signals the format is:
	<sig_name> <type> <options>

A signal must have either a @I, @O, @B, @V, or @C type as define below.  A signal
definition should be all on one line.  Lines may be broken into multiple lines
using the '\' character as described in the previous section.

Types are key letters starting with the '@' symbol.  Keyletters may be either
upper or lower case:

	o   @I
		Defines the signal as an input signal.  The qsim_sig_name is the
		signal name to use in the Qsim script as opposed to the signal
		name in the tabular file.

	o   @O
		Defines the signal as an output signal.  The qsim_sig_name is the
		signal name to use in the Qsim script as opposed to the signal
		name in the tabular file.

	o   @B <en_sig_name> <polarity>
		Defines the signal as an bidirectional signal.  The qsim_sig_name 
		is the signal name to use in the Qsim script as opposed to the signal
		name in the tabular file.  Bidirecional signals are both input
		and output signals.  The en_sig_name specifies the name of the
		*single bit* signal that controls the drive of the signal.  The
		polarity value is either 0 or 1.  If polarity is 0 this means 
		means the bidirectional signal is treated as an input signal. If
		the polarity is 1 then the signal is treated as an output signal.

	o   @C <value> ( <duration> ) ...
		Defines a clock signal.  The clock is defined as a set of value/
		duration pairs similar to the Qsim 'clock' command.  Durations
		are in nanoseconds.  Example, a 16nsec period clock with 50%
		duty cycle could be defined as: 1(8) 0(8).

	o   @DC <value> ( <duration> ) ...
		Define a clock like @C but don't echo clock definition to .sim file.
		Can still be used in @C option for other signals.

	o   @V 
		Defines the signal.  This signal will not show up as an input 
		in the Qsim script but is used to enable compares on other output 
		signals.  This signal is always logically valid, it is not 
		undefined at any time.  Valid signals are active high, when 
		the valid signal is true a compare of the actual outputs with 
		the expected output is enabled.

Options are listed below.

        o   @V <val_sig_name>
		Used with output signals.  Defines a valid signal that determines
		when a compare of actual output with expected output is valid.

	o   @E <edge_time>
		This option defines where in the cycle (in nanoseconds)
		 that the input should be applied on.  This option 
		applies only to input and bidirectional.

	o   @S <strobe_time>
		This option defines where in the cycle (in nanoseconds)
		that the output should be tested on.  This option applies only
		to output and bidirectional signals.

	o   @C <clock_name>
		This option defines which of the defined clocks the signal is 
		relative too.  Needed when multiple clocks are specified.  If
		no clock is specified, then the first clock defined is used.


//
//   Vectors
//

A vector line is simply a white-space separated group of signal values, listed from
left to right in the same order as the signal definitions are from top to bottom.
Each signal should have a corresponding field in the vector with the exception
of clock signals.  Multi-bit (bus) signals should be printed in hex format with
leading '0's, e.g. 0x0f for an 8-bit bus with a value of decimal 15.

In order to support dumps from Verilog, vector signals with [zZxX] values are
also allowed.  In these cases, however, inputs are not driven and outputs are
not tested.

If multiple clocks are used in the tab file, then the vectors must be at the rate of
the fastest clock.  The other clocks specified must be integer multiples of the
fastest clock.  The edge and strobe times for a signal is relative to the edges
of the clock option specified for the signal.