ew
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Edge Walker Unit Test Plan:
Test Cases:
NOTE: We have hit the EW pretty well with the donut test case where many
triangles were rasterized with out errors. The following list describes what
will not be tested well with other tests so we need to specialize in our
testing effort.
List of additional tests
------------------------
New 1) number of cycles EW clocks the backend is a function of
cycle type, texel size or pixel size
New 2) Hard Shutdown
Rasterization 1) we should do test 1 because it is a xy address range
test. We need to test the boundary conditions.
Rasterization 3) need to verify and determine how to place the scissor
box. off screen has negative number?
Rasterization 4) xval is all tested except for scissoring
Rasterization 6) need to verify scissoring and interlace
Attribute 2) ??? need more info
Address 1,2) max/min image size 1k x 1k or 1 x 1 and ranges. Hit some
typical cases 640x480, 320x240, maybe some prim # x,ys
Address 3) scissor address
Address 4) maximum triangle
Address 5) how many can overlap?
Address 6) ???
List of well hit cases
------------------------
Rasterization 2) should be covered well by donut
Rasterization 5) covered well
Attribute 1) should be covered well by a high frequence texture object
with many different triangles.
Timing) should be covered well by random stall tests
Comprehensive List
===============================================================================
Rasterization verification
--------------------------
inputs
------
Yh, Ym, Yl [s,11.2]
Xh, Xm, Xl [s,11.15]
DyXh, DyXm, DyXl [s,11.15]
xmin, xmax, ymin, ymax [10.2]
verification points
-------------------
x_unsc[s,11.8], x_sticky, y_cur[s,11.2], x_sc[10.3], xval[3:0], ew_cv_start_x[s,11.0], cv_new_span :
^ ^
| |
--------------- visible on ew_cv_d[12:0]
1)
vary Xh across image coord space (-2K to +2K), vary DyXh (inverse slope) from (-2K to +2K).
repeat for middle and lower edges.
when testing major edge: set Yh = large neg, Yl = large pos
when testing middle edge: set Yh = large neg, Ym = large pos
when testing lower edge: set Ym = large neg, Yl = large pos
2)
left major triangles:
a) vary Ym from subpixel 0 -> 3 to verify minor edge switch (also vary Xl subpixel 0->3)
b) repeat with Ym = Yh
c) repeat with Ym = Yl
d) repeat with Yh = Ym = Yl
e) repeat a-d with right major tri's
3)
for 1) and 2) verify scizzor box:
vary xmin[10.2] and xmax[10.2] and verify following logic:
if (x_unsc < 0)
{
clamp_xmin = 1
clamp_xmax = 0
}
else if (x_unsc >= 1024)
{
clamp_xmin = 0
clamp_xmax = 1
}
else
{
clamp_xmin = (x_unsc < xmin);
clamp_xmax = (x_unsc >= xmax);
}
if (clamp_xmin)
x_sc[10.3] = {xmin, 0};
else if (clamp_xmax)
x_sc[10.3] = {xmax, 0};
else
x_sc[10.3] = {x_unsc,sticky};
4)
verify xval[3:0]:
vary Yl, ymax, Yh, ymin to verify following equation :
xval[n] = !(y_cur >= (Yl or ymax)) && !(y_cur < (Yh or ymin));
... where n and y_cur vary from subspan 0 to 3
5)
verify ew_cv_start_x[s,11.0]:
vary left/right major and pos/neg DyXh to verify following logic :
if (left_major && DyXh == pos) || (right_major && DyXh == neg)
ew_cv_start_x[11:0] = (int) xh_unsc[0]; /* where xh_unsc means unscizzored, major edge */
else
ew_cv_start_x[11:0] = (int) xh_unsc[3];
6)
verify newspan:
vary xval[3:0] from 0x0 to 0xf, vary xmin[11:0] and xmax[11:0] to verify:
newspan = !(xval[3:0] == 0x0) && !all_less_xmin && !all_ge_xmax;
... where all_less_xmin means the entire span lies to the left of the scizzor box
and all_ge_xmax means the entire span lies to the right of the scizzor box
... also verify that span_valid is correctly calculated based on interleave mode.
Attribute Verification
----------------------
inputs
------
A[s,15.16] : attribute backed up to nearest pixel row (RGBASTWLZ)
DeA[s,15.16] : delta attribute per step along the edge (RGBASTWLZ)
DxA[s,15.16] : delta attribute per positive pixel (RGBASTWLZ)
DyA[s,15.16] : delta attribute per positive line (RGBASTWLZ)
verification points
-------------------
ew_ep_d[s,15.16], ew_ep_startspan
1)
left major triangle, DxYh = 1, top vertex on pixel center => to disable per span adjustment.
walk ones across starting attribute. walk ones across DeA. walk ones across both.
multiple primitives: run random data through A and DeA.
(repeat for RGBASTWLZ)
2)
vary sign of DyXh, and left_major to verify conditional statement:
if !((DyXh < 0) ^ left_major)
att_d_out[31:0] = att_d_in[31:0] + 3/4 * DeA - 3/4 * DyA - DxA * x_frac
else
att_d_out[31:0] = att_d_in[31:0] - DxA * x_frac
vary A, DeA, DyA, DxA, att_d_in, to verify above equations. vary x_frac by running several
different primitives with slightly different DyXh's.
3)
ew_ep_startspan = cv_new_span delayed 2 cycles
Address Verification
----------------------
verification points
-------------------
ew_ms_length[12.0], ew_ms_addr[20.0], span_overlap, memspan fifo input control ?
1)
set xmajor_sc and x_minor_sc to zero. walk ones across width and yh to verify
bit-serial multiplier. verify that addr_scanline is zero for spans in negative
image space.
2)
for multiple large tri's, vary the width to verify the addr_scanline + width add.
3)
verify x_major_sc[12.0] and x_minor_sc[12.0] => span left/right/top/bottom/straddling
scizzor box.
4)
verify that ew_ms_length[12.0] is abs(x_major_unsc - x_minor_sc) by varying span position
wrt to scizzor box.
5)
verify span_overlap = [yh(10.0) == yl_prev(10.0)]
6)
be sure that 1) through 5) test both left/right major, +/- slopes, acute/non-acute
minor edge angles.
Timing Verification
-------------------
modes:
1-cycle, 2-cycle, copy, fill (8-bit, 16-bit, 32-bit)
load_tile, load_block, load_tlut x 8-bit, 16-bit, 32-bit
for each mode:
back to back primitives with (1,2,3,4, .... n spans)
to verify stall duration, spans with 1 cycle -> n cycles (n > 9)
verify that ew_busy goes high one cycle after cs_ew_newprim and goes low coincident
with x_minor[3].