/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

// $Id: at_cc.v,v 1.1.1.1 2002/05/17 06:07:44 blythe Exp $

////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:      at_cc
// description: Attribute buffers for cc unit. Primitives data updates
//		the cycle before it is needed (via mux), but is only used
//		the following cycle. Hardware synchronized attribute data
//		is updated the cycle of the attribute (via mux), but is
//		only used the following cycle, which lines up with the
//		first cycle of a following primitive. QTV will barf on
//		this, since it will see the update cycle as not making
//		timing, while only the following cycle really matters.
//		Unsynchronized attributes update immediately, producing
//		trash for one cycle, followed by good data the next cycle.
//		The csim should generate garbage (0xDEADBEEF, for example)
//		during this trashed update cycle. Some logically synced
//		data require no special buffering because the timing
//		just works out (scissor, the EW dx's and dy's). Unsynced
//		attributes must be maintained by software, using the
//		sync_tile and sync_pipe commands after the last primitive
//		before any unsynced attribute update commands if necessary.
//
// designer:    Phil Gossett
// date:        10/24/94
//
////////////////////////////////////////////////////////////////////////

module at_cc (gclk, reset_l,
	cs_st_prim, cs_st_attr, cs_cmd, cs_ew_d,
	st_dxr, st_dxg, st_dxb, st_dxa,
	st_dyr, st_dyg, st_dyb, st_dya,
	combine_mode, env_color, prim_color,
	convert, key_r, key_gb, noise);

input gclk;
input reset_l;
input cs_st_prim;
input cs_st_attr;
input [5:0] cs_cmd;
input [63:0] cs_ew_d;

output [21:0] st_dxr;		// s10.11 (triple buffer)
output [21:0] st_dxg;		// s10.11 (triple buffer)
output [21:0] st_dxb;		// s10.11 (triple buffer)
output [21:0] st_dxa;		// s10.11 (triple buffer)
output [12:0] st_dyr;		// s10.2  (double buffer)
output [12:0] st_dyg;		// s10.2  (double buffer)
output [12:0] st_dyb;		// s10.2  (double buffer)
output [12:0] st_dya;		// s10.2  (double buffer)
output [55:0] combine_mode;	// 3c 55:0		 (unsynced)
output [55:0] env_color;	// 3b 31:0		 (unsynced)
output [55:0] prim_color;	// 3a 47:40, 39:0	 (triple buffer)
output [55:0] convert;		// 2c 53:0		 (unsynced)
output [55:0] key_r;		// 2b 27:0		 (unsynced)
output [55:0] key_gb;		// 2a 55:0		 (unsynced)
output [8:0] noise;		// pseudo-random noise	 (shift registers)

reg [28:1] rand29b;		// recirculating shift register
reg [27:1] rand28b;		// recirculating shift register
reg [26:1] rand27b;		// recirculating shift register
reg rand29q;			// recirculating shift register (ls bit)
reg rand28q;			// recirculating shift register (ls bit)
reg rand27q;			// recirculating shift register (ls bit)

wire [63:0] d_lat;		// delayed latched input
wire [7:0] code_0d;		// control pipeline input

reg [2:0] code_1d;		// pipeline for control
reg [2:0] code_2d;
reg [2:0] code_3d;
reg [2:0] code_4d;
reg [2:0] code_5d;
reg [2:0] code_6d;
reg [2:0] code_7d;
reg [2:0] code_8d;
reg [2:0] code_9d;
reg [2:0] code_10d;
reg [2:0] code_11d;
reg [2:0] code_12d;
reg [2:0] code_13d;
reg [2:0] code_14d;
reg [2:0] code_15d;
reg [2:0] code_16d;
reg [2:0] code_17d;
reg [2:0] code_18d;
reg [2:0] code_19d;
reg [2:0] code_20d;
reg [2:0] code_21d;
reg [2:0] code_22d;
reg [2:0] code_23d;
reg [2:0] code_24d;
reg [2:0] code_25d;
reg [2:0] code_26d;
reg [2:0] code_27d;
reg [2:0] code_28d;
reg [2:0] code_29d;
reg [2:0] code_30d;
reg [2:0] code_31d;
reg [2:0] code_32d;
reg [2:0] code_33d;
reg [2:0] code_34d;

wire [1:0] dxr_g;	// latch enables
wire [1:0] dxr_a_g;
wire [1:0] dxr_b_g;
wire [1:0] dxr_c_g;
wire [1:0] dxg_g;
wire [1:0] dxg_a_g;
wire [1:0] dxg_b_g;
wire [1:0] dxg_c_g;
wire [1:0] dxb_g;
wire [1:0] dxb_a_g;
wire [1:0] dxb_b_g;
wire [1:0] dxb_c_g;
wire [1:0] dxa_g;
wire [1:0] dxa_a_g;
wire [1:0] dxa_b_g;
wire [1:0] dxa_c_g;
wire [1:0] dyr_g;
wire [1:0] dyr_a_g;
wire [1:0] dyr_b_g;
wire [1:0] dyg_g;
wire [1:0] dyg_a_g;
wire [1:0] dyg_b_g;
wire [1:0] dyb_g;
wire [1:0] dyb_a_g;
wire [1:0] dyb_b_g;
wire [1:0] dya_g;
wire [1:0] dya_a_g;
wire [1:0] dya_b_g;
wire cm_g;
wire en_g;
wire pc_g;
wire pc_a_g;
wire pc_b_g;
wire pc_c_g;
wire cv_g;
wire kr_g;
wire kg_g;

wire [31:0] st_dxr_a;	// latch outputs
wire [31:0] st_dxr_b;
wire [31:0] st_dxr_c;
wire [31:0] st_dxg_a;
wire [31:0] st_dxg_b;
wire [31:0] st_dxg_c;
wire [31:0] st_dxb_a;
wire [31:0] st_dxb_b;
wire [31:0] st_dxb_c;
wire [31:0] st_dxa_a;
wire [31:0] st_dxa_b;
wire [31:0] st_dxa_c;
wire [31:0] st_dyr_a;
wire [31:0] st_dyr_b;
wire [31:0] st_dyg_a;
wire [31:0] st_dyg_b;
wire [31:0] st_dyb_a;
wire [31:0] st_dyb_b;
wire [31:0] st_dya_a;
wire [31:0] st_dya_b;
wire [55:0] combine_mode_a;
wire [55:0] env_color_a;
wire [55:0] prim_color_a;
wire [55:0] prim_color_b;
wire [55:0] prim_color_c;
wire [55:0] convert_a;
wire [55:0] key_r_a;
wire [55:0] key_gb_a;

wire dxr_s;	// read counter increment strobes
wire dxg_s;
wire dxb_s;
wire dxa_s;
wire dyr_s;
wire dyg_s;
wire dyb_s;
wire dya_s;
wire pcm_s;
wire pcl_s;

wire [1:0] dxr_sel;	// read counter selects
wire [1:0] dxg_sel;
wire [1:0] dxb_sel;
wire [1:0] dxa_sel;
wire dyr_sel;
wire dyg_sel;
wire dyb_sel;
wire dya_sel;
wire [1:0] pcm_sel;
wire [1:0] pcl_sel;

wire reset;

// invert reset (this week)
assign reset = ~reset_l;

// 3 bits worth of pseudo-random number generators
always @(posedge gclk)
begin
	// 2^29 - 1 = 536,870,911 = 233*1103*2089     = 8 seconds:
	rand29b[28:1] <= {rand29b[27:1],rand29q};
	// 2^28 - 1 = 268,435,455 = 3*5*29*43*113*127 = 4 seconds:
	rand28b[27:1] <= {rand28b[26:1],rand28q};
	// 2^27 - 1 = 134,217,727 = 7*73*262657       = 2 seconds:
	rand27b[26:1] <= {rand27b[25:1],rand27q};
end

// 3 bits worth of pseudo-random number generators (ls bit)
always @(posedge gclk or posedge reset)
begin
	if (reset == 1'b1)
		begin
		rand29q <= 1'b1;
		rand28q <= 1'b1;
		rand27q <= 1'b1;
		end
	else
		begin
		// 2^29 - 1 = 536,870,911 = 233*1103*2089     = 8 seconds:
		rand29q <= rand29b[28]^rand29b[1];
		// 2^28 - 1 = 268,435,455 = 3*5*29*43*113*127 = 4 seconds:
		rand28q <= rand28b[27]^rand28b[2];
		// 2^27 - 1 = 134,217,727 = 7*73*262657       = 2 seconds:
		rand27q <= rand27b[26]^rand27b[4]^rand27b[1]^rand27q;
		end
end

// bias to zero by adding one less than lsb of random number
assign noise = {rand29q,rand28q,rand27q,6'b100000};

// control pipeline input
assign code_0d = {cs_st_prim,cs_st_attr,cs_cmd};

// pipeline for control
always @(posedge gclk)
begin
	code_1d <= {code_0d[7], (code_0d[6:0] == 7'h7a),  // prim color
				(code_0d[6:0] == 7'h6e)}; // prim depth
	code_2d <= code_1d;
	code_3d <= code_2d;
	code_4d <= code_3d;
	code_5d <= code_4d;
	code_6d <= code_5d;
	code_7d <= code_6d;
	code_8d <= code_7d;
	code_9d <= code_8d;
	code_10d <= code_9d;
	code_11d <= code_10d;
	code_12d <= code_11d;
	code_13d <= code_12d;
	code_14d <= code_13d;
	code_15d <= code_14d;
	code_16d <= code_15d;
	code_17d <= code_16d;
	code_18d <= code_17d;
	code_19d <= code_18d;
	code_20d <= code_19d;
	code_21d <= code_20d;
	code_22d <= code_21d;
	code_23d <= code_22d;
	code_24d <= code_23d;
	code_25d <= code_24d;
	code_26d <= code_25d;
	code_27d <= code_26d;
	code_28d <= code_27d;
	code_29d <= code_28d;
	code_30d <= code_29d;
	code_31d <= code_30d;
	code_32d <= code_31d;
	code_33d <= code_32d;
	code_34d <= code_33d;
end

// generate latch enables for single buffers
assign dxr_g[1] = code_11d[2];
assign dxr_g[0] = code_10d[2];
assign dxg_g[1] = code_11d[2];
assign dxg_g[0] = code_10d[2];
assign dxb_g[1] = code_9d[2];
assign dxb_g[0] = code_8d[2];
assign dxa_g[1] = code_9d[2];
assign dxa_g[0] = code_8d[2];
assign dyr_g[1] = code_20d[2];
assign dyr_g[0] = code_19d[2];
assign dyg_g[1] = code_20d[2];
assign dyg_g[0] = code_19d[2];
assign dyb_g[1] = code_18d[2];
assign dyb_g[0] = code_17d[2];
assign dya_g[1] = code_18d[2];
assign dya_g[0] = code_17d[2];
assign cm_g     = (code_0d[6:0] == 7'h7c);
assign en_g     = (code_0d[6:0] == 7'h7b);
assign pc_g     = (code_0d[6:0] == 7'h7a);
assign cv_g     = (code_0d[6:0] == 7'h6c);
assign kr_g     = (code_0d[6:0] == 7'h6b);
assign kg_g     = (code_0d[6:0] == 7'h6a);

// generate latch enables for multi buffers
at_ctw3 ctdxrmg	(.clk(gclk), .rst(reset), .enb(dxr_g[1]),
		 .a(dxr_a_g[1]), .b(dxr_b_g[1]), .c(dxr_c_g[1]));
at_ctw3 ctdxrlg	(.clk(gclk), .rst(reset), .enb(dxr_g[0]),
		 .a(dxr_a_g[0]), .b(dxr_b_g[0]), .c(dxr_c_g[0]));
at_ctw3 ctdxgmg	(.clk(gclk), .rst(reset), .enb(dxg_g[1]),
		 .a(dxg_a_g[1]), .b(dxg_b_g[1]), .c(dxg_c_g[1]));
at_ctw3 ctdxglg	(.clk(gclk), .rst(reset), .enb(dxg_g[0]),
		 .a(dxg_a_g[0]), .b(dxg_b_g[0]), .c(dxg_c_g[0]));
at_ctw3 ctdxbmg	(.clk(gclk), .rst(reset), .enb(dxb_g[1]),
		 .a(dxb_a_g[1]), .b(dxb_b_g[1]), .c(dxb_c_g[1]));
at_ctw3 ctdxblg	(.clk(gclk), .rst(reset), .enb(dxb_g[0]),
		 .a(dxb_a_g[0]), .b(dxb_b_g[0]), .c(dxb_c_g[0]));
at_ctw3 ctdxamg	(.clk(gclk), .rst(reset), .enb(dxa_g[1]),
		 .a(dxa_a_g[1]), .b(dxa_b_g[1]), .c(dxa_c_g[1]));
at_ctw3 ctdxalg	(.clk(gclk), .rst(reset), .enb(dxa_g[0]),
		 .a(dxa_a_g[0]), .b(dxa_b_g[0]), .c(dxa_c_g[0]));
at_ctw2 ctdyrmg	(.clk(gclk), .rst(reset), .enb(dyr_g[1]),
		 .a(dyr_a_g[1]), .b(dyr_b_g[1]));
at_ctw2 ctdyrlg	(.clk(gclk), .rst(reset), .enb(dyr_g[0]),
		 .a(dyr_a_g[0]), .b(dyr_b_g[0]));
at_ctw2 ctdygmg	(.clk(gclk), .rst(reset), .enb(dyg_g[1]),
		 .a(dyg_a_g[1]), .b(dyg_b_g[1]));
at_ctw2 ctdyglg	(.clk(gclk), .rst(reset), .enb(dyg_g[0]),
		 .a(dyg_a_g[0]), .b(dyg_b_g[0]));
at_ctw2 ctdybmg	(.clk(gclk), .rst(reset), .enb(dyb_g[1]),
		 .a(dyb_a_g[1]), .b(dyb_b_g[1]));
at_ctw2 ctdyblg	(.clk(gclk), .rst(reset), .enb(dyb_g[0]),
		 .a(dyb_a_g[0]), .b(dyb_b_g[0]));
at_ctw2 ctdyamg	(.clk(gclk), .rst(reset), .enb(dya_g[1]),
		 .a(dya_a_g[1]), .b(dya_b_g[1]));
at_ctw2 ctdyalg	(.clk(gclk), .rst(reset), .enb(dya_g[0]),
		 .a(dya_a_g[0]), .b(dya_b_g[0]));
at_ctw3 pcg	(.clk(gclk), .rst(reset), .enb(pc_g),
		 .a(pc_a_g), .b(pc_b_g), .c(pc_c_g));

// instanciated latches
at_latch64 dlat   (.clkn( gclk),   .i(cs_ew_d), .z(d_lat));
at_latch32 sdxra (.clk(gclk),.g(dxr_a_g),.i({2{d_lat[31:16]}}),.z(st_dxr_a));
at_latch32 sdxrb (.clk(gclk),.g(dxr_b_g),.i({2{d_lat[31:16]}}),.z(st_dxr_b));
at_latch32 sdxrc (.clk(gclk),.g(dxr_c_g),.i({2{d_lat[31:16]}}),.z(st_dxr_c));
at_latch32 sdxga (.clk(gclk),.g(dxg_a_g),.i({2{d_lat[15: 0]}}),.z(st_dxg_a));
at_latch32 sdxgb (.clk(gclk),.g(dxg_b_g),.i({2{d_lat[15: 0]}}),.z(st_dxg_b));
at_latch32 sdxgc (.clk(gclk),.g(dxg_c_g),.i({2{d_lat[15: 0]}}),.z(st_dxg_c));
at_latch32 sdxba (.clk(gclk),.g(dxb_a_g),.i({2{d_lat[31:16]}}),.z(st_dxb_a));
at_latch32 sdxbb (.clk(gclk),.g(dxb_b_g),.i({2{d_lat[31:16]}}),.z(st_dxb_b));
at_latch32 sdxbc (.clk(gclk),.g(dxb_c_g),.i({2{d_lat[31:16]}}),.z(st_dxb_c));
at_latch32 sdxaa (.clk(gclk),.g(dxa_a_g),.i({2{d_lat[15: 0]}}),.z(st_dxa_a));
at_latch32 sdxab (.clk(gclk),.g(dxa_b_g),.i({2{d_lat[15: 0]}}),.z(st_dxa_b));
at_latch32 sdxac (.clk(gclk),.g(dxa_c_g),.i({2{d_lat[15: 0]}}),.z(st_dxa_c));
at_latch32 sdyra (.clk(gclk),.g(dyr_a_g),.i({2{d_lat[31:16]}}),.z(st_dyr_a));
at_latch32 sdyrb (.clk(gclk),.g(dyr_b_g),.i({2{d_lat[31:16]}}),.z(st_dyr_b));
at_latch32 sdyga (.clk(gclk),.g(dyg_a_g),.i({2{d_lat[15: 0]}}),.z(st_dyg_a));
at_latch32 sdygb (.clk(gclk),.g(dyg_b_g),.i({2{d_lat[15: 0]}}),.z(st_dyg_b));
at_latch32 sdyba (.clk(gclk),.g(dyb_a_g),.i({2{d_lat[31:16]}}),.z(st_dyb_a));
at_latch32 sdybb (.clk(gclk),.g(dyb_b_g),.i({2{d_lat[31:16]}}),.z(st_dyb_b));
at_latch32 sdyaa (.clk(gclk),.g(dya_a_g),.i({2{d_lat[15: 0]}}),.z(st_dya_a));
at_latch32 sdyab (.clk(gclk),.g(dya_b_g),.i({2{d_lat[15: 0]}}),.z(st_dya_b));
at_latch56 cma (.clk(gclk), .g(  cm_g), .i(d_lat[55:0]), .z(combine_mode_a));
at_latch56 ena (.clk(gclk), .g(  en_g), .i(d_lat[55:0]), .z(env_color_a));
at_latch56 pca (.clk(gclk), .g(pc_a_g), .i(d_lat[55:0]), .z(prim_color_a));
at_latch56 pcb (.clk(gclk), .g(pc_b_g), .i(d_lat[55:0]), .z(prim_color_b));
at_latch56 pcc (.clk(gclk), .g(pc_c_g), .i(d_lat[55:0]), .z(prim_color_c));
at_latch56 cva (.clk(gclk), .g(  cv_g), .i(d_lat[55:0]), .z(convert_a));
at_latch56 kra (.clk(gclk), .g(  kr_g), .i(d_lat[55:0]), .z(key_r_a));
at_latch56 kga (.clk(gclk), .g(  kg_g), .i(d_lat[55:0]), .z(key_gb_a));

// generate strobes for incrementing read pointers
assign dxr_s   = code_32d[2];				// 34
assign dxg_s   = code_32d[2];				// 34
assign dxb_s   = code_32d[2];				// 34
assign dxa_s   = code_32d[2];				// 34
assign dyr_s   = code_32d[2];				// 34
assign dyg_s   = code_32d[2];				// 34
assign dyb_s   = code_32d[2];				// 34
assign dya_s   = code_32d[2];				// 34
assign pcm_s   = code_21d[1];				// 22
assign pcl_s   = code_34d[1];				// 35

// generate read pointers for multi buffers
at_ctr3 ctdxrs	(.clk(gclk), .rst(reset), .enb(dxr_s),   .z(dxr_sel));
at_ctr3 ctdxgs	(.clk(gclk), .rst(reset), .enb(dxg_s),   .z(dxg_sel));
at_ctr3 ctdxbs	(.clk(gclk), .rst(reset), .enb(dxb_s),   .z(dxb_sel));
at_ctr3 ctdxas	(.clk(gclk), .rst(reset), .enb(dxa_s),   .z(dxa_sel));
at_ctr2 ctdyrs	(.clk(gclk), .rst(reset), .enb(dyr_s),   .z(dyr_sel));
at_ctr2 ctdygs	(.clk(gclk), .rst(reset), .enb(dyg_s),   .z(dyg_sel));
at_ctr2 ctdybs	(.clk(gclk), .rst(reset), .enb(dyb_s),   .z(dyb_sel));
at_ctr2 ctdyas	(.clk(gclk), .rst(reset), .enb(dya_s),   .z(dya_sel));
at_ctr3 pcms	(.clk(gclk), .rst(reset), .enb(pcm_s),    .z(pcm_sel));
at_ctr3 pcls	(.clk(gclk), .rst(reset), .enb(pcl_s),    .z(pcl_sel));

// read latches with bit assignments and padding (unused latches eaten)
assign st_dxr =  dxr_sel[1] ?	st_dxr_c[26:5] :		// 10.11
		(dxr_sel[0] ?	st_dxr_b[26:5] :
				st_dxr_a[26:5]);
assign st_dxg =  dxg_sel[1] ?	st_dxg_c[26:5] :
		(dxg_sel[0] ?	st_dxg_b[26:5] :
				st_dxg_a[26:5]);
assign st_dxb =  dxb_sel[1] ?	st_dxb_c[26:5] :
		(dxb_sel[0] ?	st_dxb_b[26:5] :
				st_dxb_a[26:5]);
assign st_dxa =  dxa_sel[1] ?	st_dxa_c[26:5] :
		(dxa_sel[0] ?	st_dxa_b[26:5] :
				st_dxa_a[26:5]);
assign st_dyr = dyr_sel ? st_dyr_b[26:14] : st_dyr_a[26:14];	// 10.2
assign st_dyg = dyg_sel ? st_dyg_b[26:14] : st_dyg_a[26:14];
assign st_dyb = dyb_sel ? st_dyb_b[26:14] : st_dyb_a[26:14];
assign st_dya = dya_sel ? st_dya_b[26:14] : st_dya_a[26:14];
assign combine_mode = combine_mode_a[55:0];
assign env_color = env_color_a[31:0];
assign prim_color[55:40] =	 pcm_sel[1] ?	prim_color_c[47:40] :
				(pcm_sel[0] ?	prim_color_b[47:40] :
						prim_color_a[47:40]);
assign prim_color[39:0] =	 pcl_sel[1] ?	prim_color_c[39:0] :
				(pcl_sel[0] ?	prim_color_b[39:0] :
						prim_color_a[39:0]);
assign convert = convert_a[53:0];
assign key_r = key_r_a[27:0];
assign key_gb = key_gb_a[55:0];

endmodule // at_cc