at_ew.ss 4.8 KB
/*****************************************************************************/
/* custom variables                                                          */
/*****************************************************************************/
module = "at_ew"
wire_load = 256000
standard_load = 0.01
clock = "gclk"
default_input_delay = 1.5
default_output_delay = 14.0
default_input_load = 20
default_output_load = 20
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 1.0

hdlin_force_use_ffgen = false


/*****************************************************************************/
/* set the path and read                                                     */
/*****************************************************************************/
search_path = search_path \
   + "../src" \
   + "../../inc" \
   + "../../../lib/verilog/user" \
   + "../../syn"

read -f verilog at_latch_l.v
read -f verilog at_latch_h.v
read -f verilog at_latch1.v
read -f verilog at_latch23.v
read -f verilog at_latch32.v
read -f verilog at_latch56.v
read -f verilog at_latch64.v
read -f verilog at_ctrn.v
read -f verilog at_ctrb.v
read -f verilog module + ".v"


/*****************************************************************************/
/* default environment                                                       */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top


/*****************************************************************************/
/* clock and reset constraints                                               */
/*****************************************************************************/
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clock
set_dont_touch_network clock


/*****************************************************************************/
/* default constraint                                                        */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }

set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null

set_drive 0 { clock }
set_input_delay 0 { clock }

set_max_transition default_max_transition current_design


/*****************************************************************************/
/* custom constraints                                                        */
/*****************************************************************************/
set_output_delay 0.0 -clock clock ew_dxr
set_output_delay 0.0 -clock clock ew_dxg
set_output_delay 0.0 -clock clock ew_dxb
set_output_delay 0.0 -clock clock ew_dxa
set_output_delay 0.0 -clock clock ew_dxz
set_output_delay 0.0 -clock clock ew_dxs
set_output_delay 0.0 -clock clock ew_dxt
set_output_delay 0.0 -clock clock ew_dxw
set_output_delay 0.0 -clock clock ew_dxl
set_output_delay 0.0 -clock clock ew_dyr
set_output_delay 0.0 -clock clock ew_dyg
set_output_delay 0.0 -clock clock ew_dyb
set_output_delay 0.0 -clock clock ew_dya
set_output_delay 0.0 -clock clock ew_dyz
set_output_delay 0.0 -clock clock ew_dys
set_output_delay 0.0 -clock clock ew_dyt
set_output_delay 0.0 -clock clock ew_dyw
set_output_delay 0.0 -clock clock ew_dyl
set_output_delay 0.0 -clock clock scissor
set_output_delay 0.0 -clock clock ew_image_load

set_false_path -fall -from reset_l
set_max_fanout 2 * standard_load reset_l


/*****************************************************************************/
/* check                                                                     */
/*****************************************************************************/
check_design > module + ".lint"


/*****************************************************************************/
/* compile                                                                   */
/*****************************************************************************/
ungroup -all -flatten
set_register_type -latch lanfnh -exact find(cell, dlat/l/q_reg*)
compile -ungroup_all


/*****************************************************************************/
/* write                                                                     */
/*****************************************************************************/
include "report.dc"

change_names -rules compass_rules -hierarchy
write -format edif -hierarchy -o module + ".edf" module
write -format db -hierarchy -o module + ".db" module
quit