ep_cc.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: ep_cc.v,v 1.1.1.1 2002/05/17 06:07:45 blythe Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: ep_cc
// description: Top level for edge walker pipe.
//
// designer: Phil Gossett
// date: 12/6/94
//
////////////////////////////////////////////////////////////////////////
module ep_cc (gclk, cycle_type,
st_span_5d, d_3d, cv_x_offset, cv_y_offset, cv_cvg, cv_mask,
st_span_st_r, st_span_st_g, st_span_st_b, st_span_st_a,
st_span_st_z, st_span_tf, st_span_cc, st_span_bl, st_span_ms,
d_r, d_g, d_b, d_a, d_z,
x_offset_r, x_offset_g, x_offset_b, x_offset_a, x_offset_z,
y_offset_r, y_offset_g, y_offset_b, y_offset_a, y_offset_z,
cvg_cc, mask_bl);
input gclk;
input [1:0] cycle_type;
input st_span_5d;
input [21:0] d_3d;
input [1:0] cv_x_offset;
input [1:0] cv_y_offset;
input [3:0] cv_cvg;
input cv_mask;
output st_span_st_r;
output st_span_st_g;
output st_span_st_b;
output st_span_st_a;
output st_span_st_z;
output st_span_tf;
output st_span_cc;
output st_span_bl;
output st_span_ms;
output [21:0] d_r;
output [21:0] d_g;
output [21:0] d_b;
output [21:0] d_a;
output [21:0] d_z;
output [1:0] x_offset_r;
output [1:0] x_offset_g;
output [1:0] x_offset_b;
output [1:0] x_offset_a;
output [1:0] x_offset_z;
output [1:0] y_offset_r;
output [1:0] y_offset_g;
output [1:0] y_offset_b;
output [1:0] y_offset_a;
output [1:0] y_offset_z;
output [3:0] cvg_cc;
output mask_bl;
reg st_span_6d;
reg st_span_7d;
reg st_span_8d;
reg st_span_9d;
reg st_span_10d;
reg st_span_11d;
reg st_span_12d;
reg st_span_13d;
reg st_span_14d;
reg st_span_15d;
reg st_span_16d;
reg st_span_17d;
reg st_span_18d;
reg st_span_19d;
reg st_span_20d;
reg st_span_21d;
reg [21:0] d_4d;
reg [21:0] d_5d;
reg [21:0] d_6d;
reg [21:0] d_7d;
reg [21:0] d_8d;
reg [21:0] d_9d;
reg [21:0] d_10d;
reg [1:0] x_offset_1d;
reg [1:0] x_offset_2d;
reg [1:0] x_offset_3d;
reg [1:0] x_offset_4d;
reg [1:0] x_offset_5d;
reg [1:0] x_offset_6d;
reg [1:0] x_offset_7d;
reg [1:0] x_offset_8d;
reg [1:0] x_offset_9d;
reg [1:0] x_offset_10d;
reg [1:0] x_offset_11d;
reg [1:0] x_offset_12d;
reg [1:0] x_offset_13d;
reg [1:0] x_offset_14d;
reg [1:0] x_offset_15d;
reg [1:0] x_offset_16d;
reg [1:0] x_offset_17d;
reg [1:0] x_offset_18d;
reg [1:0] x_offset_19d;
reg [1:0] x_offset_20d;
reg [1:0] x_offset_21d;
reg [1:0] x_offset_22d;
reg [1:0] y_offset_1d;
reg [1:0] y_offset_2d;
reg [1:0] y_offset_3d;
reg [1:0] y_offset_4d;
reg [1:0] y_offset_5d;
reg [1:0] y_offset_6d;
reg [1:0] y_offset_7d;
reg [1:0] y_offset_8d;
reg [1:0] y_offset_9d;
reg [1:0] y_offset_10d;
reg [1:0] y_offset_11d;
reg [1:0] y_offset_12d;
reg [1:0] y_offset_13d;
reg [1:0] y_offset_14d;
reg [1:0] y_offset_15d;
reg [1:0] y_offset_16d;
reg [1:0] y_offset_17d;
reg [1:0] y_offset_18d;
reg [1:0] y_offset_19d;
reg [1:0] y_offset_20d;
reg [1:0] y_offset_21d;
reg [1:0] y_offset_22d;
reg [3:0] cvg_1d;
reg [3:0] cvg_2d;
reg [3:0] cvg_3d;
reg [3:0] cvg_4d;
reg [3:0] cvg_5d;
reg [3:0] cvg_6d;
reg [3:0] cvg_7d;
reg [3:0] cvg_8d;
reg [3:0] cvg_9d;
reg [3:0] cvg_10d;
reg [3:0] cvg_11d;
reg [3:0] cvg_12d;
reg [3:0] cvg_13d;
reg [3:0] cvg_14d;
reg [3:0] cvg_15d;
reg [3:0] cvg_16d;
reg [3:0] cvg_17d;
reg [3:0] cvg_18d;
reg [3:0] cvg_19d;
reg [3:0] cvg_20d;
reg [3:0] cvg_21d;
reg mask_1d;
reg mask_2d;
reg mask_3d;
reg mask_4d;
reg mask_5d;
reg mask_6d;
reg mask_7d;
reg mask_8d;
reg mask_9d;
reg mask_10d;
reg mask_11d;
reg mask_12d;
reg mask_13d;
reg mask_14d;
reg mask_15d;
reg mask_16d;
reg mask_17d;
reg mask_18d;
reg mask_19d;
reg mask_20d;
reg mask_21d;
reg mask_22d;
reg mask_23d;
reg mask_24d;
wire two_cyc;
always @(posedge gclk)
begin
st_span_6d <= st_span_5d;
st_span_7d <= st_span_6d;
st_span_8d <= st_span_7d;
st_span_9d <= st_span_8d;
st_span_10d <= st_span_9d;
st_span_11d <= st_span_10d;
st_span_12d <= st_span_11d;
st_span_13d <= st_span_12d;
st_span_14d <= st_span_13d;
st_span_15d <= st_span_14d;
st_span_16d <= st_span_15d;
st_span_17d <= st_span_16d;
st_span_18d <= st_span_17d;
st_span_19d <= st_span_18d;
st_span_20d <= st_span_19d;
st_span_21d <= st_span_20d;
d_4d <= d_3d;
d_5d <= d_4d;
d_6d <= d_5d;
d_7d <= d_6d;
d_8d <= d_7d;
d_9d <= d_8d;
d_10d <= d_9d;
x_offset_1d <= cv_x_offset;
x_offset_2d <= x_offset_1d;
x_offset_3d <= x_offset_2d;
x_offset_4d <= x_offset_3d;
x_offset_5d <= x_offset_4d;
x_offset_6d <= x_offset_5d;
x_offset_7d <= x_offset_6d;
x_offset_8d <= x_offset_7d;
x_offset_9d <= x_offset_8d;
x_offset_10d <= x_offset_9d;
x_offset_11d <= x_offset_10d;
x_offset_12d <= x_offset_11d;
x_offset_13d <= x_offset_12d;
x_offset_14d <= x_offset_13d;
x_offset_15d <= x_offset_14d;
x_offset_16d <= x_offset_15d;
x_offset_17d <= x_offset_16d;
x_offset_18d <= x_offset_17d;
x_offset_19d <= x_offset_18d;
x_offset_20d <= x_offset_19d;
x_offset_21d <= x_offset_20d;
x_offset_22d <= x_offset_21d;
y_offset_1d <= cv_y_offset;
y_offset_2d <= y_offset_1d;
y_offset_3d <= y_offset_2d;
y_offset_4d <= y_offset_3d;
y_offset_5d <= y_offset_4d;
y_offset_6d <= y_offset_5d;
y_offset_7d <= y_offset_6d;
y_offset_8d <= y_offset_7d;
y_offset_9d <= y_offset_8d;
y_offset_10d <= y_offset_9d;
y_offset_11d <= y_offset_10d;
y_offset_12d <= y_offset_11d;
y_offset_13d <= y_offset_12d;
y_offset_14d <= y_offset_13d;
y_offset_15d <= y_offset_14d;
y_offset_16d <= y_offset_15d;
y_offset_17d <= y_offset_16d;
y_offset_18d <= y_offset_17d;
y_offset_19d <= y_offset_18d;
y_offset_20d <= y_offset_19d;
y_offset_21d <= y_offset_20d;
y_offset_22d <= y_offset_21d;
cvg_1d <= cv_cvg;
cvg_2d <= cvg_1d;
cvg_3d <= cvg_2d;
cvg_4d <= cvg_3d;
cvg_5d <= cvg_4d;
cvg_6d <= cvg_5d;
cvg_7d <= cvg_6d;
cvg_8d <= cvg_7d;
cvg_9d <= cvg_8d;
cvg_10d <= cvg_9d;
cvg_11d <= cvg_10d;
cvg_12d <= cvg_11d;
cvg_13d <= cvg_12d;
cvg_14d <= cvg_13d;
cvg_15d <= cvg_14d;
cvg_16d <= cvg_15d;
cvg_17d <= cvg_16d;
cvg_18d <= cvg_17d;
cvg_19d <= cvg_18d;
cvg_20d <= cvg_19d;
cvg_21d <= cvg_20d;
mask_1d <= cv_mask;
mask_2d <= mask_1d;
mask_3d <= mask_2d;
mask_4d <= mask_3d;
mask_5d <= mask_4d;
mask_6d <= mask_5d;
mask_7d <= mask_6d;
mask_8d <= mask_7d;
mask_9d <= mask_8d;
mask_10d <= mask_9d;
mask_11d <= mask_10d;
mask_12d <= mask_11d;
mask_13d <= mask_12d;
mask_14d <= mask_13d;
mask_15d <= mask_14d;
mask_16d <= mask_15d;
mask_17d <= mask_16d;
mask_18d <= mask_17d;
mask_19d <= mask_18d;
mask_20d <= mask_19d;
mask_21d <= mask_20d;
mask_22d <= mask_21d;
mask_23d <= mask_22d;
mask_24d <= mask_23d;
end
assign two_cyc = (cycle_type == 1);
assign st_span_st_r = st_span_18d;
assign st_span_st_g = st_span_18d;
assign st_span_st_b = st_span_18d;
assign st_span_st_a = st_span_18d;
assign st_span_st_z = two_cyc ? st_span_21d : st_span_20d;
assign st_span_tf = st_span_16d;
assign st_span_cc = st_span_18d;
assign st_span_bl = two_cyc ? st_span_21d : st_span_20d;
assign st_span_ms = st_span_6d; // 3 before load, 4 before copy
// 10 before 1 cyc, 12 before 2 cyc
assign d_r = d_10d;
assign d_g = d_9d;
assign d_b = d_8d;
assign d_a = d_7d;
assign d_z = two_cyc ? d_9d : d_8d;
assign x_offset_r = x_offset_19d;
assign x_offset_g = x_offset_19d;
assign x_offset_b = x_offset_19d;
assign x_offset_a = x_offset_19d;
assign x_offset_z = two_cyc ? x_offset_22d : x_offset_21d;
assign y_offset_r = y_offset_19d;
assign y_offset_g = y_offset_19d;
assign y_offset_b = y_offset_19d;
assign y_offset_a = y_offset_19d;
assign y_offset_z = two_cyc ? y_offset_22d : y_offset_21d;
assign cvg_cc = cvg_21d;
assign mask_bl = two_cyc ? mask_24d : mask_23d;
endmodule // ep_cc