ms_latch144.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: ms_latch144.v,v 1.1.1.1 2002/05/17 06:07:47 blythe Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: ms_latch144
// description: Transparent latches: spanbuf output, transp=~clk
//
// designer: Mike M. Cai / Robert W. Sherburne
// date: 12/16/94 revised 1/6/95
//
////////////////////////////////////////////////////////////////////////
module ms_latch144 (d_out, clk, g, d_in);
output [143:0] d_out;
input [143:0] d_in;
input clk, g;
wire [7:0] d_0, d_1, d_2, d_3, d_4, d_5, d_6, d_7, d_8,
d_9, d_a, d_b, d_c, d_d, d_e, d_f, d_g, d_h;
wire [7:0] q_0, q_1, q_2, q_3, q_4, q_5, q_6, q_7, q_8,
q_9, q_a, q_b, q_c, q_d, q_e, q_f, q_g, q_h;
wire e_0, e_1, e_2, e_3, e_4, e_5, e_6, e_7, e_8,
e_9, e_a, e_b, e_c, e_d, e_e, e_f, e_g, e_h;
wire gn;
assign {d_h, d_g, d_f, d_e, d_d, d_c, d_b, d_a, d_9,
d_8, d_7, d_6, d_5, d_4, d_3, d_2, d_1, d_0} = d_in;
assign d_out = {q_h, q_g, q_f, q_e, q_d, q_c, q_b, q_a, q_9,
q_8, q_7, q_6, q_5, q_4, q_3, q_2, q_1, q_0};
in01d5 in_0(.i(g), .zn(gn));
nr02d2 nr_0(.a1(clk), .a2(gn), .zn(e_0));
nr02d2 nr_1(.a1(clk), .a2(gn), .zn(e_1));
nr02d2 nr_2(.a1(clk), .a2(gn), .zn(e_2));
nr02d2 nr_3(.a1(clk), .a2(gn), .zn(e_3));
nr02d2 nr_4(.a1(clk), .a2(gn), .zn(e_4));
nr02d2 nr_5(.a1(clk), .a2(gn), .zn(e_5));
nr02d2 nr_6(.a1(clk), .a2(gn), .zn(e_6));
nr02d2 nr_7(.a1(clk), .a2(gn), .zn(e_7));
nr02d2 nr_8(.a1(clk), .a2(gn), .zn(e_8));
nr02d2 nr_9(.a1(clk), .a2(gn), .zn(e_9));
nr02d2 nr_a(.a1(clk), .a2(gn), .zn(e_a));
nr02d2 nr_b(.a1(clk), .a2(gn), .zn(e_b));
nr02d2 nr_c(.a1(clk), .a2(gn), .zn(e_c));
nr02d2 nr_d(.a1(clk), .a2(gn), .zn(e_d));
nr02d2 nr_e(.a1(clk), .a2(gn), .zn(e_e));
nr02d2 nr_f(.a1(clk), .a2(gn), .zn(e_f));
nr02d2 nr_g(.a1(clk), .a2(gn), .zn(e_g));
nr02d2 nr_h(.a1(clk), .a2(gn), .zn(e_h));
ms_latch_h #(8) l_0(.e(e_0), .d(d_0), .q(q_0));
ms_latch_h #(8) l_1(.e(e_1), .d(d_1), .q(q_1));
ms_latch_h #(8) l_2(.e(e_2), .d(d_2), .q(q_2));
ms_latch_h #(8) l_3(.e(e_3), .d(d_3), .q(q_3));
ms_latch_h #(8) l_4(.e(e_4), .d(d_4), .q(q_4));
ms_latch_h #(8) l_5(.e(e_5), .d(d_5), .q(q_5));
ms_latch_h #(8) l_6(.e(e_6), .d(d_6), .q(q_6));
ms_latch_h #(8) l_7(.e(e_7), .d(d_7), .q(q_7));
ms_latch_h #(8) l_8(.e(e_8), .d(d_8), .q(q_8));
ms_latch_h #(8) l_9(.e(e_9), .d(d_9), .q(q_9));
ms_latch_h #(8) l_a(.e(e_a), .d(d_a), .q(q_a));
ms_latch_h #(8) l_b(.e(e_b), .d(d_b), .q(q_b));
ms_latch_h #(8) l_c(.e(e_c), .d(d_c), .q(q_c));
ms_latch_h #(8) l_d(.e(e_d), .d(d_d), .q(q_d));
ms_latch_h #(8) l_e(.e(e_e), .d(d_e), .q(q_e));
ms_latch_h #(8) l_f(.e(e_f), .d(d_f), .q(q_f));
ms_latch_h #(8) l_g(.e(e_g), .d(d_g), .q(q_g));
ms_latch_h #(8) l_h(.e(e_h), .d(d_h), .q(q_h));
endmodule //