ms_latch72.v 2.46 KB
 /**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

// $Id: ms_latch72.v,v 1.1.1.1 2002/05/17 06:07:47 blythe Exp $

////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:      ms_latch72
// description: Transparent latches:  rdram to spanbuf, transp=clk
//
// designer:    Mike M. Cai / Robert W. Sherburne
// date:        12/16/94 revised 1/6/95
//
////////////////////////////////////////////////////////////////////////

module ms_latch72 (d_out, clk, g, d_in);
output [71:0] 	  d_out;
input [71:0]  	  d_in;
input 	       	  clk, g;

wire [7:0] d_0, d_1, d_2, d_3, d_4, d_5, d_6, d_7, d_8;
wire [7:0] q_0, q_1, q_2, q_3, q_4, q_5, q_6, q_7, q_8;
wire e_0, e_1, e_2, e_3, e_4, e_5, e_6, e_7, e_8;
wire gn;

assign {d_8, d_7, d_6, d_5, d_4, d_3, d_2, d_1, d_0} = d_in;
assign d_out = {q_8, q_7, q_6, q_5, q_4, q_3, q_2, q_1, q_0};

ni01d5 in_0(.i(g), .z(gn));

an02d2 an_0(.a1(clk), .a2(gn), .z(e_0));
an02d2 an_1(.a1(clk), .a2(gn), .z(e_1));
an02d2 an_2(.a1(clk), .a2(gn), .z(e_2));
an02d2 an_3(.a1(clk), .a2(gn), .z(e_3));
an02d2 an_4(.a1(clk), .a2(gn), .z(e_4));
an02d2 an_5(.a1(clk), .a2(gn), .z(e_5));
an02d2 an_6(.a1(clk), .a2(gn), .z(e_6));
an02d2 an_7(.a1(clk), .a2(gn), .z(e_7));
an02d2 an_8(.a1(clk), .a2(gn), .z(e_8));

ms_latch_h #(8) l_0(.e(e_0), .d(d_0), .q(q_0));
ms_latch_h #(8) l_1(.e(e_1), .d(d_1), .q(q_1));
ms_latch_h #(8) l_2(.e(e_2), .d(d_2), .q(q_2));
ms_latch_h #(8) l_3(.e(e_3), .d(d_3), .q(q_3));
ms_latch_h #(8) l_4(.e(e_4), .d(d_4), .q(q_4));
ms_latch_h #(8) l_5(.e(e_5), .d(d_5), .q(q_5));
ms_latch_h #(8) l_6(.e(e_6), .d(d_6), .q(q_6));
ms_latch_h #(8) l_7(.e(e_7), .d(d_7), .q(q_7));
ms_latch_h #(8) l_8(.e(e_8), .d(d_8), .q(q_8));

endmodule //