/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/


// $Id: si_pchclk.v,v 1.1.1.1 2002/05/17 06:07:48 blythe Exp $

module si_pchclk(clk, reset_l, pchclk, div_cnt);

input clk;          // system clock
input reset_l;      // system reset

output pchclk;      // pchannel clock source
output [1:0] div_cnt ;


// output registers
reg pchclk;
reg [1:0] div_cnt;

wire ctr_clr_pulse;

// internal regs
reg reset_l_d1;
reg reset_l_d2;

always @( posedge clk) begin
    reset_l_d1 <= reset_l;
    reset_l_d2 <= reset_l_d1;
end

// reset must be brought hi for at least one clock
// to allow hi to low edge detect 
assign ctr_clr_pulse = (~reset_l_d1 & reset_l_d2) ;

always @(posedge clk or posedge ctr_clr_pulse) begin
    if (ctr_clr_pulse == 1'b1) begin
        // clear cntr for consistent test vector operation
        div_cnt <= 2'b00;
    end
    else begin
        div_cnt <= (div_cnt + 1) ;
    end

end // always


// create pchannel clock from decode of counter
always @(posedge clk ) begin

    if ((div_cnt == 2'b11) | (div_cnt == 2'b0) ) begin
        pchclk <= 1;
    end
    else begin
        pchclk <= 0;
    end
end // always

        
endmodule