si_pif_if.v
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/************************************************************************\
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
\************************************************************************/
//////////////////////////////////////////////////////////////////////
// --- pchannel serial input output interface
//
// $Id: si_pif_if.v,v 1.1.1.1 2002/05/17 06:07:48 blythe Exp $
module si_pif_if(pchclk, pch_reg_msb, pch_cmd_valid, pch_rsp_in,
pch_cmd_reg, pch_rsp_reg, pch_rsp_reg_d1,pif_clk);
input pchclk;
input pch_reg_msb;
input pch_cmd_valid;
input pch_rsp_in;
output pch_cmd_reg;
output pch_rsp_reg;
output pch_rsp_reg_d1;
output pif_clk;
wire pchclk;
wire pch_reg_msb;
wire pch_cmd_valid;
wire pch_rsp_in;
wire pch_cmd_reg;
wire pch_rsp_reg;
wire pch_rsp_reg_d1;
wire pif_clk;
wire pch_cmd_reg_bufin;
wire pch_reg_msb_bar;
wire pch_cmd_inp;
wire pchclk_i1;
//
// serial input output interface registers on pchclk domain
in01d1 in01d1_0 (.i(pch_reg_msb) , .zn(pch_reg_msb_bar) );
nd02d1 nd02d1_0 (.zn(pch_cmd_inp), .a1 (pch_reg_msb_bar), .a2(pch_cmd_valid));
dfntnh dfntnh_0 (.q(pch_cmd_reg_bufin) , .d(pch_cmd_inp), .cp(pchclk) );
ni01d5 ni01d5_0 (.z(pch_cmd_reg) , .i(pch_cmd_reg_bufin) );
dfntnb dfntnb_1 (.q(pch_rsp_reg) , .d(pch_rsp_in), .cp(pchclk) );
dfntnb dfntnb_2 (.q(pch_rsp_reg_d1) , .d(pch_rsp_reg), .cp(pchclk) );
// delay external pif_clk relative to internal pif clock.
in01d3 in01d3_0 (.i(pchclk) , .zn(pchclk_i1) );
in01d5 in01d5_0 (.i(pchclk_i1) , .zn(pif_clk) );
endmodule