/************************************************************************\
 *                                                                        *
 *               Copyright(C) 1994, Silicon Graphics, Inc.                *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: rcp.v,v 1.1.1.1 2002/05/17 06:07:48 blythe Exp $

`timescale 1ns/1ns

module rcp(mclock_pad, reset_l_pad, test_pad,
   p_valid_pad, e_valid_pad, e_ok_pad, int_pad, sys_ad_pad, sys_cmd_pad,
   tx_clk, v_ref, c_ctl_pgm, rx_clk,
   bus_enable_rac, bus_ctrl_rac, bus_data_rac,
   ad16_aleh_pad, ad16_alel_pad, ad16_read_pad, ad16_write_pad, ad16_data_pad,
   pif_rsp_pad, pif_cmd_pad, pif_clock_pad,
   abus_data_pad, abus_word_pad, abus_clock_pad,
   vbus_data_pad, vbus_sync_pad, vclk_pad);

`include "rcp.vh"

output mclock_pad;
input reset_l_pad;
input test_pad;

// R4200B interface
input p_valid_pad;
output e_valid_pad;
output e_ok_pad;
output int_pad;
inout [SYS_AD_SIZE-1:0] sys_ad_pad;
inout [SYS_CMD_SIZE-1:0] sys_cmd_pad;

// Rambus interface
input tx_clk;
input v_ref;
input c_ctl_pgm;
output rx_clk;
output bus_enable_rac;
inout bus_ctrl_rac;
inout [RAMBUS_DATA_SIZE-1:0] bus_data_rac;

// AD 16 interface
output ad16_aleh_pad;
output ad16_alel_pad;
output ad16_read_pad;
output ad16_write_pad;
inout [AD16_DATA_SIZE-1:0] ad16_data_pad;

// PIF interface
input pif_rsp_pad;
output pif_cmd_pad;
output pif_clock_pad;

// ABUS interface
output abus_data_pad;
output abus_word_pad;
output abus_clock_pad;

// VBUS interface
output [VBUS_DATA_SIZE-1:0] vbus_data_pad;
output vbus_sync_pad;
inout vclk_pad;

supply0 gnd;
supply1 vcc;

// system interface
wire clock;
wire gclk;
wire vclk;
wire reset_l;
wire start_gclk;
wire test;
wire test_pad;


// R4200B interface
wire p_valid_l;
wire e_valid_l;
wire e_ok_l;
wire int_l;
wire [SYS_AD_SIZE-1:0] sys_ad_out;
wire [SYS_AD_SIZE-1:0] sys_ad_in;
wire [SYS_CMD_SIZE-1:0] sys_cmd_out;
wire [SYS_CMD_SIZE-1:0] sys_cmd_in;
wire [4:0] sys_ad_enable_l;

// AD 16 signals
wire ad16_aleh;
wire ad16_alel;
wire ad16_read_l;
wire ad16_write_l;
wire ad16_enable_l;
wire tst_ad16_read_l;
wire tst_ad16_write_l;
wire [1:0] tst_ad16_enable_l;
wire [AD16_DATA_SIZE-1:0] ad16_data_in;
wire [AD16_DATA_SIZE-1:0] ad16_data_out;

// PIF signals
wire pif_rsp;
wire pif_cmd;
wire pif_clock;

// ABUS signals
wire abus_data;
wire abus_word;
wire abus_clock;

// VBUS signals
wire [VBUS_DATA_SIZE-1:0] vbus_data;
wire vbus_sync;
wire [VBUS_DATA_SIZE-1:0] vbus_data_reg;
wire vbus_sync_reg;
wire vclk_in;
wire vclk_out;
wire vclk_enable_l;

// RAC signals
wire [RAC_RECEIVE_DATA_SIZE-1:0] r_data_7, r_data_6, r_data_5, r_data_4;
wire [RAC_RECEIVE_DATA_SIZE-1:0] r_data_3, r_data_2, r_data_1, r_data_0;
wire syn_clk, syn_clk_fd;
wire bist_flag, scan_out;
wire bus_clk;
wire [RAC_SELECT_SIZE-1:0] bd_sel, bc_sel, be_sel, rd_sel, rc_sel;
wire [RAC_TRANSMIT_DATA_SIZE-1:0] t_data_7, t_data_6, t_data_5, t_data_4;
wire [RAC_TRANSMIT_DATA_SIZE-1:0] t_data_3, t_data_2, t_data_1, t_data_0;
wire v_ref;
wire bist_mode, iost_mode, scan_mode, scan_clk, scan_en, scan_in, syn_clk_in;
wire c_ctl_en, c_ctl_ld;
wire [RAC_CURRENT_SIZE-1:0] c_ctl_i;
wire tst_c_ctl_en, tst_c_ctl_ld;
wire [RAC_CURRENT_SIZE-1:0] tst_c_ctl_i;
wire c_ctl_pgm, pwr_up, ext_be, stop_r, stop_t;
wire by_pass, by_p_sel, rclk_asic, tclk_asic, ph_stall;
wire rac_reset;
wire ack, nack;

// rbus signals
wire [RBUS_DATA_SIZE-1:0] rbus_data_in;
wire [RBUS_EXTEND_SIZE-1:0] rbus_extend_in;
wire [RBUS_CONTROL_SIZE-1:0] rbus_control_in;
wire [RBUS_DATA_SIZE-1:0] rbus_data_out;
wire [RBUS_EXTEND_SIZE-1:0] rbus_extend_out;
wire [RBUS_CONTROL_SIZE-1:0] rbus_control_out;
wire [RBUS_ENABLE_SIZE-1:0] rbus_enable_out;
wire [RAC_SELECT_SIZE-1:0] rac_sel_in;
wire [RAC_SELECT_SIZE-1:0] rac_sel_out;

// ARB and DMA signals
wire dma_ready;
wire dma_start;
wire dma_last;
wire xbus_valid;

wire sp_cbus_read_enable;
wire sp_cbus_write_enable;
wire sp_dma_grant;
wire sp_read_grant;
wire sp_dbus_read_enable;
wire sp_dbus_write_enable;
wire sp_dma_request;
wire sp_read_request;
wire sp_interrupt;

wire mem_read_request;
wire mem_cbus_read_enable;
wire mem_cbus_write_enable;

wire cmd_cbus_read_enable;
wire cmd_cbus_write_enable;
wire cmd_dma_grant;
wire cmd_read_grant;
wire cmd_dma_request;
wire cmd_read_request;

wire mi_dma_request;
wire mi_write_request;
wire mi_read_request;
wire mi_cbus_read_enable;
wire mi_cbus_write_enable;
wire mi_cbus_grant;
wire mi_dbus_read_enable;
wire mi_dbus_write_enable;

wire pi_dbus_write_enable;
wire pi_cbus_read_enable;
wire pi_cbus_write_enable;
wire pi_dma_grant;
wire pi_read_grant;
wire pi_dma_request;
wire pi_read_request;
wire pi_interrupt;

wire si_dbus_write_enable;
wire si_cbus_read_enable;
wire si_cbus_write_enable;
wire si_dma_grant;
wire si_read_grant;
wire si_dma_request;
wire si_read_request;
wire si_interrupt;

wire ai_cbus_read_enable;
wire ai_cbus_write_enable;
wire ai_dma_grant;
wire ai_read_grant;
wire ai_dma_request;
wire ai_read_request;
wire ai_interrupt;

wire vi_cbus_read_enable;
wire vi_cbus_write_enable;
wire vi_dma_grant;
wire vi_read_grant;
wire vi_dma_request;
wire vi_read_request;
wire vi_interrupt;

wire span_dbus_read_enable;
wire span_dbus_write_enable;
wire span_cbus_read_enable;
wire span_cbus_write_enable;
wire span_dma_grant;
wire span_read_grant;
wire span_dma_request;
wire span_read_request;

wire ri_read_request;
wire ri_read_grant;

wire cbuf_ready;
wire cbuf_write;

wire [CBUS_COMMAND_SIZE-1:0] cbus_command;
wire [CBUS_SELECT_SIZE-1:0] cbus_select;
wire [CBUS_DATA_SIZE-1:0] cbus_data;
wire [DBUS_DATA_SIZE-1:0] dbus_data;
wire [EBUS_DATA_SIZE-1:0] ebus_data;
wire [XBUS_DATA_SIZE-1:0] xbus_data;

wire cmd_busy;
wire pipe_busy;
wire tmem_busy;

wire flush;
wire freeze;
wire unfreeze;
wire refresh_strobe;
wire iddq_test;
wire reset_l_0;
wire reset_l_1;
wire reset_l_2;
wire reset_l_3;
wire reset_l_4;
wire reset_l_5;
wire reset_l_6;
wire reset_l_7;
wire reset_l_8;
wire reset_l_9;

wire [CBUS_DATA_SIZE-1:0] version = RCP_VERSION;


pad pad_0(
   // System Interface
   .synclk_in(syn_clk),
   .mclk_pad(mclock_pad),
   .reset_out(reset_l),
   .reset_pad(reset_l_pad),
   .test_out(test),
   .test_pad(test_pad),

   .start_gclk(start_gclk),
   .clk(clock),
   .gclk(gclk),

   // SysAD Interface
   .pvalid_out(p_valid_l),
   .pvalid_pad(p_valid_pad),
   .evalid_in(e_valid_l),
   .evalid_pad(e_valid_pad),
   .eok_in(e_ok_l),
   .eok_pad(e_ok_pad),
   .int_in(int_l),
   .int_pad(int_pad),
   .sysad_out(sys_ad_in),
   .sysad_in(sys_ad_out),
   .sysad_pad(sys_ad_pad),
   .syscmd_out(sys_cmd_in),
   .syscmd_in(sys_cmd_out),
   .syscmd_pad(sys_cmd_pad),
   .sysad_en_l(sys_ad_enable_l),

   // AD16 Interface
   .cartaleh_in(ad16_aleh),
   .cartaleh_pad(ad16_aleh_pad),
   .cartalel_in(ad16_alel),
   .cartalel_pad(ad16_alel_pad),
   .cartrd_in(tst_ad16_read_l),
   .cartrd_pad(ad16_read_pad),
   .cartwr_in(tst_ad16_write_l),
   .cartwr_pad(ad16_write_pad),
   .cartad_out(ad16_data_in),
   .cartad_in(ad16_data_out),
   .cartad_pad(ad16_data_pad),
   .cartad_en_l(tst_ad16_enable_l),

   // PIF Interface
   .pifrsp_out(pif_rsp),
   .pifrsp_pad(pif_rsp_pad),
   .pifcmd_in(pif_cmd),
   .pifcmd_pad(pif_cmd_pad),
   .pifclk_in(pif_clock),
   .pifclk_pad(pif_clock_pad),

   // Audio Interface
   .auddata_in(abus_data),
   .auddata_pad(abus_data_pad),
   .audclk_in(abus_clock),
   .audclk_pad(abus_clock_pad),
   .audlrclk_in(abus_word),
   .audlrclk_pad(abus_word_pad),

   // Video Interface
   .srgba_in(vbus_data_reg),
   .srgba_pad(vbus_data_pad),
   .vsync_in(vbus_sync_reg),
   .vsync_pad(vbus_sync_pad),
   .vclk_in(clock),
   .vclk_out(vclk_in),
   .vclk_pad(vclk_pad),
   .vclk_en_l(vclk_enable_l));

rsp rsp_0(
   .clk(clock),
   .reset_l(reset_l_0),
   .iddq_test(iddq_test),
   .sp_cbus_read_enable(sp_cbus_read_enable),
   .sp_cbus_write_enable(sp_cbus_write_enable),
   .mem_cbus_write_enable(mem_cbus_write_enable),
   .cmd_cbus_read_enable(cmd_cbus_read_enable),
   .cmd_cbus_write_enable(cmd_cbus_write_enable),
   .cbus_select(cbus_select),
   .cbus_command(cbus_command),
   .dma_start(dma_start),
   .dma_last(dma_last),
   .sp_dma_grant(sp_dma_grant),
   .sp_read_grant(sp_read_grant),
   .cmd_dma_grant(cmd_dma_grant),
   .cmd_read_grant(cmd_read_grant),
   .sp_dbus_read_enable(sp_dbus_read_enable),
   .sp_dbus_write_enable(sp_dbus_write_enable),
   .cbuf_ready(cbuf_ready),
   .cmd_busy(cmd_busy),
   .pipe_busy(pipe_busy),
   .tmem_busy(tmem_busy),
   .frozen(start_gclk),
   .sp_dma_request(sp_dma_request),
   .sp_read_request(sp_read_request),
   .mem_read_request(mem_read_request),
   .cmd_dma_request(cmd_dma_request),
   .cmd_read_request(cmd_read_request),
   .cbuf_write(cbuf_write),
   .flush(flush),
   .freeze(freeze),
   .unfreeze(unfreeze),
   .sp_interrupt(sp_interrupt),
   .xbus_data(xbus_data),
   .cbus_data(cbus_data),
   .dbus_data(dbus_data));

rdp rdp_0(
   .clk(clock),
   .gclk(gclk),
   .reset_l(reset_l_0),
   .iddq(iddq_test),
   .cbus_write_enable(span_cbus_write_enable),
   .cbus_read_enable(span_cbus_read_enable),
   .cbus_select(cbus_select),
   .cbus_command(cbus_command),
   .xbus_cs_data(xbus_data),
   .xbus_cs_valid(cbuf_write),
   .flush(flush),
   .freeze(freeze),
   .unfreeze(unfreeze),
   .grant(span_dma_grant),
   .start(dma_start),
   .finish(dma_last),
   .read_grant(span_read_grant),
   .dma_write_enable(span_dbus_write_enable),
   .dma_read_enable(span_dbus_read_enable),
   .cs_xbus_req(cbuf_ready),
   .start_gclk(start_gclk),
   .rdramreq(span_dma_request),
   .read_request(span_read_request),
   .cmd_busy(cmd_busy),
   .pipe_busy(pipe_busy),
   .tmem_busy(tmem_busy),
   .cbus_data(cbus_data),
   .dbus_data(dbus_data),
   .ebus_data(ebus_data));

mi mi_0(
   .clock(clock),
   .reset_l(reset_l_0),
   .cbus_read_enable(mi_cbus_read_enable),
   .cbus_write_enable(mi_cbus_write_enable),
   .cbus_grant(mi_cbus_grant),
   .dbus_read_enable(mi_dbus_read_enable),
   .dbus_write_enable(mi_dbus_write_enable),
   .dma_start(dma_start),
   .dma_last(dma_last),
   .sys_ad_in_h(sys_ad_in),
   .sys_cmd_in_h(sys_cmd_in),
   .p_valid_l(p_valid_l),
   .cbus_select(cbus_select),
   .cbus_command(cbus_command),
   .pi_interrupt(pi_interrupt),
   .vi_interrupt(vi_interrupt),
   .ai_interrupt(ai_interrupt),
   .si_interrupt(si_interrupt),
   .sp_interrupt(sp_interrupt),
   .pipe_busy(pipe_busy),
   .version(version),
   .dma_request(mi_dma_request),
   .write_request(mi_write_request),
   .read_request(mi_read_request),
   .sys_ad_out_h(sys_ad_out),
   .sys_cmd_out_h(sys_cmd_out),
   .e_valid_l(e_valid_l),
   .e_ok_l(e_ok_l),
   .int_l(int_l),
   .sys_ad_enable_l(sys_ad_enable_l),
   .cbus_data(cbus_data),
   .dbus_data(dbus_data),
   .ebus_data(ebus_data));

pi pi_0(
   .clock(clock),
   .reset_l(reset_l_0),
   .cbus_read_enable(pi_cbus_read_enable),
   .cbus_write_enable(pi_cbus_write_enable),
   .cbus_select(cbus_select),
   .cbus_command(cbus_command),
   .dma_start(dma_start),
   .dma_last(dma_last),
   .dbus_enable(pi_dbus_write_enable),
   .dma_grant(pi_dma_grant),
   .read_grant(pi_read_grant),
   .ad16_data_in(ad16_data_in),
   .dma_request(pi_dma_request),
   .read_request(pi_read_request),
   .pi_interrupt(pi_interrupt),
   .ad16_aleh(ad16_aleh),
   .ad16_alel(ad16_alel),
   .ad16_read_l(ad16_read_l),
   .ad16_write_l(ad16_write_l),
   .ad16_enable_l(ad16_enable_l),
   .ad16_data_out(ad16_data_out),
   .cbus_data(cbus_data),
   .dbus_data(dbus_data));

si si_0(
   .clk(clock),
   .reset_l(reset_l_0),
   .cbus_read_enable(si_cbus_read_enable),
   .cbus_write_enable(si_cbus_write_enable),
   .cbus_select(cbus_select),
   .cbus_command(cbus_command),
   .dma_start(dma_start),
   .dbus_enable(si_dbus_write_enable),
   .dma_grant(si_dma_grant),
   .read_grant(si_read_grant),
   .pif_rsp(pif_rsp),
   .dma_request(si_dma_request),
   .read_request(si_read_request),
   .pif_cmd(pif_cmd),
   .pif_clk(pif_clock),
   .interrupt(si_interrupt),
   .cbus_data(cbus_data),
   .dbus_data(dbus_data));

ai ai_0(
   .clock(clock),
   .reset_l(reset_l_0),
   .cbus_read_enable(ai_cbus_read_enable),
   .cbus_write_enable(ai_cbus_write_enable),
   .cbus_select(cbus_select),
   .cbus_command(cbus_command),
   .dma_start(dma_start),
   .dma_grant(ai_dma_grant),
   .read_grant(ai_read_grant),
   .dbus_data(dbus_data),
   .vbus_clock(vclk),
   .dma_request(ai_dma_request),
   .read_request(ai_read_request),
   .abus_data(abus_data),
   .abus_word(abus_word),
   .abus_clock(abus_clock),
   .ai_full(ai_interrupt),
   .cbus_data(cbus_data));

vi vi_0(
   .clk(clock),
   .vclk(vclk),
   .reset_l(reset_l_0),
   .cbus_read_enable(vi_cbus_read_enable),
   .cbus_write_enable(vi_cbus_write_enable),
   .cbus_select(cbus_select),
   .cbus_command(cbus_command),
   .dma_start(dma_start),
   .dma_last(dma_last),
   .dma_grant(vi_dma_grant),
   .read_grant(vi_read_grant),
   .dma_request(vi_dma_request),
   .read_request(vi_read_request),
   .vbus_data(vbus_data),
   .vbus_sync(vbus_sync),
   .vbus_clock_enable_l(vclk_enable_l),
   .vi_int(vi_interrupt),
   .refresh_strobe(refresh_strobe),
   .cbus_data(cbus_data),
   .dbus_data(dbus_data),
   .ebus_data(ebus_data));

arb arb_0(
   .clock(clock),
   .reset_l(reset_l_0),
   .dma_ready(dma_ready),
   .sp_dma_request(sp_dma_request),
   .sp_read_request(sp_read_request),
   .mem_read_request(mem_read_request),
   .mi_dma_request(mi_dma_request),
   .mi_write_request(mi_write_request),
   .mi_read_request(mi_read_request),
   .cmd_dma_request(cmd_dma_request),
   .cmd_read_request(cmd_read_request),
   .ri_read_request(ri_read_request),
   .pi_dma_request(pi_dma_request),
   .pi_read_request(pi_read_request),
   .si_dma_request(si_dma_request),
   .si_read_request(si_read_request),
   .ai_dma_request(ai_dma_request),
   .ai_read_request(ai_read_request),
   .vi_dma_request(vi_dma_request),
   .vi_read_request(vi_read_request),
   .span_dma_request(span_dma_request),
   .span_read_request(span_read_request),
   .refresh_strobe(refresh_strobe),
   .sp_cbus_read_enable(sp_cbus_read_enable),
   .sp_cbus_write_enable(sp_cbus_write_enable),
   .sp_dma_grant(sp_dma_grant),
   .sp_read_grant(sp_read_grant),
   .mem_cbus_write_enable(mem_cbus_write_enable),
   .mi_cbus_read_enable(mi_cbus_read_enable),
   .mi_cbus_write_enable(mi_cbus_write_enable),
   .mi_cbus_grant(mi_cbus_grant),
   .cmd_cbus_read_enable(cmd_cbus_read_enable),
   .cmd_cbus_write_enable(cmd_cbus_write_enable),
   .cmd_dma_grant(cmd_dma_grant),
   .cmd_read_grant(cmd_read_grant),
   .ri_cbus_read_enable(ri_cbus_read_enable),
   .ri_cbus_write_enable(ri_cbus_write_enable),
   .ri_read_grant(ri_read_grant),
   .pi_cbus_read_enable(pi_cbus_read_enable),
   .pi_cbus_write_enable(pi_cbus_write_enable),
   .pi_dma_grant(pi_dma_grant),
   .pi_read_grant(pi_read_grant),
   .si_cbus_read_enable(si_cbus_read_enable),
   .si_cbus_write_enable(si_cbus_write_enable),
   .si_dma_grant(si_dma_grant),
   .si_read_grant(si_read_grant),
   .ai_cbus_read_enable(ai_cbus_read_enable),
   .ai_cbus_write_enable(ai_cbus_write_enable),
   .ai_dma_grant(ai_dma_grant),
   .ai_read_grant(ai_read_grant),
   .vi_cbus_read_enable(vi_cbus_read_enable),
   .vi_cbus_write_enable(vi_cbus_write_enable),
   .vi_dma_grant(vi_dma_grant),
   .vi_read_grant(vi_read_grant),
   .span_cbus_read_enable(span_cbus_read_enable),
   .span_cbus_write_enable(span_cbus_write_enable),
   .span_dma_grant(span_dma_grant),
   .span_read_grant(span_read_grant),
   .cbus_select(cbus_select),
   .cbus_command(cbus_command));

ri ri_0(
   .clock(clock),
   .reset_l(reset_l_0),
   .cbus_read_enable(ri_cbus_read_enable),
   .cbus_write_enable(ri_cbus_write_enable),
   .cbus_command(cbus_command),
   .read_grant(ri_read_grant),
   .rbus_data_in(rbus_data_in),
   .rbus_extend_in(rbus_extend_in),
   .ack(ack),
   .nack(nack),
   .tst_c_ctl_en(tst_c_ctl_en),
   .tst_c_ctl_ld(tst_c_ctl_ld),
   .tst_c_ctl_i(tst_c_ctl_i),
   .ready(dma_ready),
   .start(dma_start),
   .last(dma_last),
   .read_request(ri_read_request),
   .sp_dbus_read_enable(sp_dbus_read_enable),
   .mi_dbus_read_enable(mi_dbus_read_enable),
   .span_dbus_read_enable(span_dbus_read_enable),
   .sp_dbus_write_enable(sp_dbus_write_enable),
   .mi_dbus_write_enable(mi_dbus_write_enable),
   .pi_dbus_write_enable(pi_dbus_write_enable),
   .si_dbus_write_enable(si_dbus_write_enable),
   .span_dbus_write_enable(span_dbus_write_enable),
   .rbus_data_out(rbus_data_out),
   .rbus_extend_out(rbus_extend_out),
   .rbus_control_out(rbus_control_out),
   .rbus_enable_out(rbus_enable_out),
   .c_ctl_en(c_ctl_en),
   .c_ctl_ld(c_ctl_ld),
   .c_ctl_i(c_ctl_i),
   .rac_sel_in(rac_sel_in),
   .rac_sel_out(rac_sel_out),
   .stop_t(stop_t),
   .stop_r(stop_r),
   .cbus_data(cbus_data),
   .dbus_data(dbus_data),
   .ebus_data(ebus_data));

tst tst_0(
   .clock(clock),
   .pad_reset_l(reset_l),
   .test(test),
   .ad16_data_in(ad16_data_in[14:0]),
   .tst_ad16_enable_l_0(tst_ad16_enable_l[0]),
   .tst_ad16_enable_l_1(tst_ad16_enable_l[1]),
   .tst_ad16_read_l(tst_ad16_read_l),
   .tst_ad16_write_l(tst_ad16_write_l),
   .ad16_enable_l(ad16_enable_l),
   .ad16_read_l(ad16_read_l),
   .ad16_write_l(ad16_write_l),
   .bist_flag(bist_flag),
   .tst_by_pass(by_pass),
   .tst_bist_mode(bist_mode),
   .tst_iost_mode(iost_mode),
   .tst_rac_reset(rac_reset),
   .tst_ext_be(ext_be),
   .tst_c_ctl_en(tst_c_ctl_en),
   .tst_c_ctl_i(tst_c_ctl_i),	
   .tst_c_ctl_ld(tst_c_ctl_ld),
   .tst_synclk_set(tst_synclk_set),
   .tst_pwr_up(pwr_up),
   .tst_idd_test(iddq_test),
   .tst_reset_l_0(reset_l_0),
   .tst_reset_l_1(reset_l_1),
   .tst_reset_l_2(reset_l_2),
   .tst_reset_l_3(reset_l_3),
   .tst_reset_l_4(reset_l_4),
   .tst_reset_l_5(reset_l_5),
   .tst_reset_l_6(reset_l_6),
   .tst_reset_l_7(reset_l_7),
   .tst_reset_l_8(reset_l_8),
   .tst_reset_l_9(reset_l_9));

vclk_driver vclk_driver_0(
   .vclk_in(vclk_in),
   .reset_l(reset_l_0),
   .vbus_data(vbus_data),
   .vbus_sync(vbus_sync),
   .vbus_data_reg(vbus_data_reg),
   .vbus_sync_reg(vbus_sync_reg),
   .vclk(vclk));

rac rac_0(
   .RData7(r_data_7),
   .RData6(r_data_6),
   .RData5(r_data_5),
   .RData4(r_data_4),
   .RData3(r_data_3),
   .RData2(r_data_2),
   .RData1(r_data_1),
   .RData0(r_data_0),
   .SynClk(syn_clk),
   .SynClkFd(syn_clk_fd),
   .BusEnable(bus_enable_rac),
   .BISTFlag(bist_flag),
   .SCANOut(scan_out),
   .BusCtrl(bus_ctrl_rac),
   .BusData(bus_data_rac),
   .BusClk(bus_clk),
   .BDSel(rac_sel_out),
   .BCSel(rac_sel_out),
   .BESel(rac_sel_out),
   .RDSel(rac_sel_in),
   .RCSel(rac_sel_in),
   .Reset(rac_reset),
   .TData7(t_data_7),
   .TData6(t_data_6),
   .TData5(t_data_5),
   .TData4(t_data_4),
   .TData3(t_data_3),
   .TData2(t_data_2),
   .TData1(t_data_1),
   .TData0(t_data_0),
   .Vref(v_ref),
   .BISTMode(bist_mode),
   .IOSTMode(iost_mode),
   .SCANMode(scan_mode),
   .SCANClk(scan_clk),
   .SCANEn(scan_en),
   .SCANIn(scan_in),
   .SynClkIn(syn_clk_in),
   .CCtlEn(c_ctl_en),
   .CCtlLd(c_ctl_ld),
   .CCtlI(c_ctl_i),
   .CCtlPgm(c_ctl_pgm),
   .PwrUp(pwr_up),
   .ExtBE(ext_be),
   .StopR(stop_r),
   .StopT(stop_t),
   .ByPass(by_pass),
   .ByPSel(by_p_sel),
   .rclkASIC(rclk_asic),
   .tclkASIC(tclk_asic),
   .PhStall(ph_stall));

an02d1 g_0(
   .a1(syn_clk_fd),
   .a2(tst_synclk_set),
   .z(syn_clk_in));

// bus reassignments
assign rx_clk = tx_clk;
assign bus_clk = tx_clk;
assign {rbus_control_in[0], rbus_extend_in[0], rbus_data_in[ 7: 0]} = r_data_7;
assign {rbus_control_in[1], rbus_extend_in[1], rbus_data_in[15: 8]} = r_data_6;
assign {rbus_control_in[2], rbus_extend_in[2], rbus_data_in[23:16]} = r_data_5;
assign {rbus_control_in[3], rbus_extend_in[3], rbus_data_in[31:24]} = r_data_4;
assign {rbus_control_in[4], rbus_extend_in[4], rbus_data_in[39:32]} = r_data_3;
assign {rbus_control_in[5], rbus_extend_in[5], rbus_data_in[47:40]} = r_data_2;
assign {rbus_control_in[6], rbus_extend_in[6], rbus_data_in[55:48]} = r_data_1;
assign {rbus_control_in[7], rbus_extend_in[7], rbus_data_in[63:56]} = r_data_0;

assign t_data_7 = {rbus_enable_out[0], rbus_control_out[0], rbus_extend_out[0],
  rbus_data_out[ 7: 0]};
assign t_data_6 = {rbus_enable_out[1], rbus_control_out[1], rbus_extend_out[1],
  rbus_data_out[15: 8]};
assign t_data_5 = {rbus_enable_out[2], rbus_control_out[2], rbus_extend_out[2],
  rbus_data_out[23:16]};
assign t_data_4 = {rbus_enable_out[3], rbus_control_out[3], rbus_extend_out[3],
  rbus_data_out[31:24]};
assign t_data_3 = {rbus_enable_out[4], rbus_control_out[4], rbus_extend_out[4],
  rbus_data_out[39:32]};
assign t_data_2 = {rbus_enable_out[5], rbus_control_out[5], rbus_extend_out[5],
  rbus_data_out[47:40]};
assign t_data_1 = {rbus_enable_out[6], rbus_control_out[6], rbus_extend_out[6],
  rbus_data_out[55:48]};
assign t_data_0 = {rbus_enable_out[7], rbus_control_out[7], rbus_extend_out[7],
  rbus_data_out[63:56]};

assign ack = rbus_control_in[7];
assign nack = rbus_control_in[2];
assign scan_mode = gnd;
assign scan_clk = gnd;
assign scan_en = gnd;
assign scan_in = gnd;
assign by_p_sel = vcc;
assign rclk_asic = gnd;
assign tclk_asic = gnd;
assign ph_stall = gnd;

endmodule