/* setup aliases */

alias set_default_operating_conditions \
	"set_operating_conditions NOM -library rcp.db; \
	set_wire_load 256000 -mode top;"
alias set_default_timing_constraints \
	"create_clock clk -period 14.0 -waveform {0 8.0}; \
	set_input_delay 4.0 -clock clk all_inputs(); \
	set_output_delay -max -clock clk 2.0 all_outputs(); \
	set_max_delay 14.0 -to all_outputs(); \
	set_load 0.2 all_outputs();"

/* setup the search path for includes */
search_path = search_path + "../src"

/* read the verilog sources */

read -f verilog ../../rsp/src/regfile_decode.v

current_design = regfile_decode

set_default_operating_conditions
set_default_timing_constraints

set_max_fanout 10 current_design;
set_max_transition 1.0 current_design;

set_dont_touch  address_buf2
set_dont_touch  address_buf1
set_dont_touch  address_bufcopy2
set_dont_touch  address_bufcopy1

set_dont_touch  rf_decode_1ststg

set_dont_touch  rf_decode_0to6
set_dont_touch  rf_decode_1to7
set_dont_touch  rf_decode_8to14
set_dont_touch  rf_decode_9to15
set_dont_touch  rf_decode_16to22
set_dont_touch  rf_decode_17to23
set_dont_touch  rf_decode_24to30
set_dont_touch  rf_decode_25to31

include regfile_decode.con
link 
check_design > regfile_decode.lint

compile -map_effort high -ungroup_all

report -reference 
report_constraint -all_violators 
report_timing -path full -delay max -max_paths 10 

write -f edif -o regfile_decode.edf -hier regfile_decode

quit