/* setup aliases */

alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
				        set_wire_load 512000 -mode top;"

alias set_default_timing_constraints "max_delay 5.0 -to all_outputs(); \
				      set_load 2.0 all_outputs();"

/* read the verilog sources */

read -f verilog ../src/vt_decode.v

current_design = vt_decode

set_dont_touch { ne35hd130d/ni01d* }
ungroup -flatten vt_*

set_default_operating_conditions
set_default_timing_constraints

link 

check_design > vt_decode.lint

report -reference
report_constraint -all_violators
report_timing -path full -delay max -max_paths 10
report_timing -path full -from {vt_vt_rd_inst_h_sel,vt_rd_inst_l_sel} -delay max -max_paths 10;

write -format edif -hierarchy -o vt_decode.edf vt_decode
write -format verilog -hierarchy -o vt_decode.vsyn vt_decode
write -format db -hierarchy -o vt_decode.db vt_decode

quit