iu.ress
3.44 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
/* setup aliases */
alias set_default_operating_conditions \
"set_operating_conditions NOM -library rcp.db; \
set_wire_load 256000 -mode top;"
alias set_default_timing_constraints \
"create_clock clk -period 14.0 -waveform {0 7.0}; \
set_input_delay 1.5 -clock clk all_inputs(); \
set_output_delay 1.0 -clock clk all_outputs(); \
set_clock_skew -uncertainty 1 clk; \
fix_hold clk; \
dont_touch_network clk; \
set_drive 0 {clk}; \
set_load 2 all_outputs();"
module = iu
search_path = search_path + "../src" + "../../inc" + \
"../../../lib/verilog/user" + "../../syn"
/* read the compiled rsp module netlists */
/* read -f edif /hosts/jax/a/Reality/rcp/layout/iu/iu.edf */
read -f edif iu.edf
current_design = iu
/* ungroup -all -flatten */
set_default_operating_conditions
set_default_timing_constraints
set_max_transition 2.5 current_design;
/* set_max_fanout 10 current_design; */
link
/* set realistic constraints for iu block */
include iu.con
/* include iu.load */
include iu.load
set_dont_touch sudp
set_dont_touch imem
check_design > iu.lint
/* enforce naming restrictions for Compass tools */
/* change_names -rules compass_rules -hierarchy */
/* set back-annotated capacitances on all nodes prior to resynopsys */
current_design = iu
/* standard reports & netlist */
/* include "report.dc" */
/* report_net > iu.net */
current_design = iu
/* report_constraint -all_violators */
compile_disable_area_opt_during_inplace_opt = true
compile_inplace_changed_list_file_name = inplace_changes
compile_ok_to_buffer_during_inplace_opt = false
compile_ignore_footprint_during_inplace_opt = false
compile_ignore_area_during_inplace_opt = false
/*
* Set loads here for nodes which go between the
* suctl and sudp since the iu.load file only
* has wire load and no datapath therefore
* capacitance on these nodes is smaller than
* it should be. We want to prevent
* compile -in_place from down-grading drivers
* on these nodes.
*/
set_load 2.5 su/surfile_ra_t[*]
set_load 2.5 su/surfile_ra_f[*]
set_load 2.5 su/surfile_rb_t[*]
set_load 2.5 su/surfile_rb_f[*]
set_load 2.5 su/surdamux[*]
set_load 2.5 su/surdbmux[*]
set_load 2.5 su/suimmmux[*]
set_load 2.5 su/suimmlsmux[*]
set_load 2.5 su/suvulsoffsetmux[*]
set_load 2.5 su/sualuamux[*]
set_load 2.5 su/sualubmux[*]
set_load 2.5 su/sushamux[*]
set_load 2.5 su/sushbmux[*]
set_load 2.5 su/sudrivels
set_load 2.5 su/suslten
set_load 2.5 su/susltlt
set_load 2.5 su/sualuen
set_load 2.5 su/sualu[*]
set_load 2.5 su/sushen
set_load 2.5 su/shiftamt[*]
set_load 2.5 su/surfile_w_t[*]
set_load 2.5 su/surfile_w_f[*]
set_load 2.5 su/su_mem_wen
set_load 2.5 su/suwben
set_load 2.3 su/su_inst[22]
set_load 1.1 su/su_inst[31]
set_load 2 su/su_inst_6
set_load 2 su/su_inst_15
set_load 2 all_outputs()
set_max_transition 1 all_outputs()
set_dont_touch su/vt_decode/su_inst_buf_6
set_dont_touch su/vt_decode/su_inst_buf_15
report_timing -path full -delay max -max_paths 5;
compile -in_place
report -reference
/* report_constraint -all_violators */
report_timing -path full -delay max -max_paths 5;
set_disable_timing imem
report_timing -path full -delay max -max_paths 5;
current_design = iu
compile -in_place
report -reference
/* report_constraint -all_violators */
report_timing -path full -delay max -max_paths 5;
disable_timing -restore imem
report_timing -path full -delay max -max_paths 5;
/* standard reports & netlist */
/* include "report.dc" */
write -f edif -o iu.edf -hier iu
write -f db -o iu.db -hier iu
quit