/* setup aliases */

alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
				        set_wire_load 128000 -mode top;"
alias set_default_timing_constraints "create_clock gclk -period 12.0 -waveform {0 6.0}; \
				      set_input_delay 2.0 -clock gclk all_inputs(); \
				      set_output_delay 2.0 -clock gclk all_outputs(); \
				      max_delay 2.0 -to all_outputs(); \
				      set_load 0.2 all_outputs();"

/* set up a new search path */
search_path = search_path + "../../inc"

/* read the verilog sources */
read -f verilog ../src/tc_div.v

current_design = tc_div

set_default_operating_conditions
set_default_timing_constraints

set_driving_cell -none { gclk }
set_drive 0 { gclk }
set_dont_touch_network { gclk }
set_arrival 0 gclk
set_dont_use {ne35hd130d/mbnfnq ne35hd130d/mbnfnr}
set_input_delay 5.0 -clock gclk w

max_area 0

link 

check_design > tc_div.lint


current_design = tc_div_nrmtlu
set_default_operating_conditions
max_delay 8.0 -to all_outputs()
set_load 0.2 all_outputs()
compile -map_effort high -ungroup_all
set_dont_touch current_design

current_design = tc_div_mul1
set_default_operating_conditions
max_delay 12.0 -to all_outputs()
set_load 0.2 all_outputs()
compile -map_effort high -ungroup_all -incremental_mapping
set_dont_touch current_design

current_design = tc_div_mul2
set_default_operating_conditions
max_delay 12.0 -to all_outputs()
set_load 0.2 all_outputs()
compile -map_effort high -ungroup_all -incremental_mapping
set_dont_touch current_design

current_design = tc_div_dnrmclmp
set_default_operating_conditions
max_delay 1.0 -to all_outputs()
set_load 0.2 all_outputs()
compile -map_effort high -ungroup_all -incremental_mapping
set_dont_touch current_design

current_design = tc_div
set_default_operating_conditions
set_default_timing_constraints
compile -map_effort high -ungroup_all
set_dont_touch current_design


report -reference

report_constraint -all_violators

write -f edif -o tc_div.edf -hier tc_div

quit