tc_frac.ss
1.76 KB
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/* setup aliases */
alias set_default_operating_conditions "set_operating_conditions NOM -library rcp.db; \
set_wire_load 128000 -mode top;"
alias set_default_timing_constraints "create_clock gclk -period 14.0 -waveform {0 8.0}; \
set_input_delay 2.0 -clock gclk all_inputs(); \
set_output_delay 2.0 -clock gclk all_outputs(); \
max_delay 2.0 -to all_outputs(); \
set_load 0.2 all_outputs();"
/* set up a new search path */
search_path = search_path + "../../inc"
/* read the verilog sources */
read -f verilog ../src/tc_frac.v
current_design = tc_frac
set_driving_cell -none { gclk }
set_drive 0 { gclk }
set_dont_touch_network { gclk }
set_arrival 0 gclk
set_dont_use {ne35hd130d/mbnfnq ne35hd130d/mbnfnr}
max_area 0
link
check_design > tc_frac.lint
compile -map_effort low -ungroup_all
/* set timing constraints */
set_default_operating_conditions
create_clock gclk -period 18.0 -waveform {9.0 18.0}
set_max_transition 3.0 current_design;
set_input_delay 2.0 -clock gclk all_inputs();
set_driving_cell -cell dfntnh all_inputs();
set_output_delay 2.0 -clock gclk all_outputs()
set_load 0.08 all_outputs()
set_driving_cell -none {gclk}
set_drive 0 {gclk}
/* fix s_frac, t_frac grounded outputs */
set_unconnected s_frac_rg_out[2]
set_unconnected s_frac_rg_out[1]
set_unconnected s_frac_rg_out[0]
set_unconnected s_frac_ba_out[2]
set_unconnected s_frac_ba_out[1]
set_unconnected s_frac_ba_out[0]
set_unconnected t_frac_rg_out[2]
set_unconnected t_frac_rg_out[1]
set_unconnected t_frac_rg_out[0]
set_unconnected t_frac_ba_out[2]
set_unconnected t_frac_ba_out[1]
set_unconnected t_frac_ba_out[0]
compile -map_effort high -ungroup_all
report -reference
report_constraint -all_violators
write -f edif -o tc_frac.edf -hier tc_frac
quit