vi_rand.v
3.98 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: vi_rand.v,v 1.1.1.1 2002/05/17 06:07:49 blythe Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: vi_rand
// description: Pseudo_random number generator for video interface unit.
// Generates six bits of pseudo-random numbers for
// dithering the 8 bit linear RGB values to 7 bit
// gamma corrected. Made of long period recirculating shift
// registers, with relatively prime periods for each of the
// six bits. Should be run off the video clock, so
// will not correlate with noise or dithering in the rdp.
//
// designer: Phil Gossett
// date: 9/25/94
//
////////////////////////////////////////////////////////////////////////
module vi_rand (vclk, reset_l, rand);
input vclk;
input reset_l;
output [5:0] rand;
wire reset;
reg [28:1] rand29b; // recirculating shift register
reg [26:1] rand27b; // recirculating shift register
reg [24:1] rand25b; // recirculating shift register
reg [22:1] rand23b; // recirculating shift register
reg [18:1] rand19b; // recirculating shift register
reg [16:1] rand17b; // recirculating shift register
reg rand29q; // recirculating shift register (ls bit)
reg rand27q; // recirculating shift register (ls bit)
reg rand25q; // recirculating shift register (ls bit)
reg rand23q; // recirculating shift register (ls bit)
reg rand19q; // recirculating shift register (ls bit)
reg rand17q; // recirculating shift register (ls bit)
// invert reset (this week)
assign reset = ~reset_l;
// 6 bits worth of pseudo-random number generators
always @(posedge vclk)
begin
// 2^29 - 1 = 536,870,911 = 233*1103*2089 = 10 s
rand29b[28:1] <= {rand29b[27:1],rand29q};
// 2^27 - 1 = 134,217,727 = 7*73*262657 = 2 s
rand27b[26:1] <= {rand27b[25:1],rand27q};
// 2^25 - 1 = 33,554,431 = 31*601*1801 = 640 ms
rand25b[24:1] <= {rand25b[23:1],rand25q};
// 2^23 - 1 = 8,388,607 = 47*178481 = 160 ms
rand23b[22:1] <= {rand23b[21:1],rand23q};
// 2^19 - 1 = 524,287 = 524287 = 10 ms
rand19b[18:1] <= {rand19b[17:1],rand19q};
// 2^17 - 1 = 131,071 = 131071 = 2 ms
rand17b[16:1] <= {rand17b[15:1],rand17q};
end
// 6 bits worth of pseudo-random number generators (ls bit)
always @(posedge vclk or posedge reset)
begin
if (reset == 1'b1)
begin
rand29q <= 1'b1;
rand27q <= 1'b1;
rand25q <= 1'b1;
rand23q <= 1'b1;
rand19q <= 1'b1;
rand17q <= 1'b1;
end
else
begin
// 2^29 - 1 = 536,870,911 = 233*1103*2089 = 10 s
rand29q <= rand29b[28]^rand29b[1];
// 2^27 - 1 = 134,217,727 = 7*73*262657 = 2 s:
rand27q <= rand27b[26]^rand27b[4]^rand27b[1]^rand27q;
// 2^25 - 1 = 33,554,431 = 31*601*1801 = 640 ms
rand25q <= rand25b[24]^rand25b[2];
// 2^23 - 1 = 8,388,607 = 47*178481 = 160 ms
rand23q <= rand23b[22]^rand23b[4];
// 2^19 - 1 = 524,287 = 524287 = 10 ms
rand19q <= rand19b[18]^rand19b[4]^rand19b[1]^rand19q;
// 2^17 - 1 = 131,071 = 131071 = 2 ms
rand17q <= rand17b[16]^rand17b[2];
end
end
// concatenate to form dither value
assign rand = {rand29q,rand27q,rand25q,rand23q,rand19q,rand17q};
endmodule // vi_rand