vi_lerp.ss 4.21 KB
/*****************************************************************************/
/* custom variables                                                          */
/*****************************************************************************/
module = vi_lerp
wire_load = 256000
standard_load = 0.01
clock = vclk
default_input_delay = 1.5
default_output_delay = 14.0
default_input_load = 20
default_output_load = 20
default_drive_cell = dfntnh
default_drive_pin = q
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 0.5

hdlin_force_use_ffgen = false


/*****************************************************************************/
/* set the path and read                                                     */
/*****************************************************************************/
search_path = search_path + "../src" + "../../syn"

read -f verilog ../src/vi_lerp.v
read -f verilog ../src/vi_lerp_booth.v
read -f verilog ../src/vi_lerp_booth0.v
read -f verilog ../src/vi_lerp_booth7.v
read -f verilog ../src/vi_lerp_csa.v
read -f verilog ../src/vi_lerp_csa_add10.v
read -f verilog ../src/vi_lerp_csa_fa4.v
read -f verilog ../src/vi_lerp_csa_fa5.v
read -f verilog ../src/vi_lerp_csa_fa6.v
read -f verilog ../src/vi_lerp_csa_ha1.v
read -f verilog ../src/vi_lerp_csa_ha2.v
read -f verilog ../src/vi_lerp_csa_ha3.v
read -f verilog ../src/vi_lerp_csa_haco.v
read -f verilog ../src/vi_lerp_csa_haso.v

current_design = module


/*****************************************************************************/
/* default environment                                                       */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top


/*****************************************************************************/
/* clock constraints                                                         */
/*****************************************************************************/
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clock
set_dont_touch_network clock


/*****************************************************************************/
/* default constraint                                                        */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }

set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null

set_drive 0 clock

set_max_transition default_max_transition current_design


/*****************************************************************************/
/* custom constraints                                                        */
/*****************************************************************************/


/*****************************************************************************/
/* check                                                                     */
/*****************************************************************************/
link
check_design > module + ".lint"


/*****************************************************************************/
/* compile                                                                   */
/*****************************************************************************/
set_dont_touch vlbooth true
set_dont_touch vlcsa true

compile -no_map -ungroup_all

set_dont_touch vlbooth false
set_dont_touch vlcsa false

compile -map_effort high -ungroup_all -incremental_mapping


/*****************************************************************************/
/* write                                                                     */
/*****************************************************************************/
include "report.dc"

change_names -rules compass_rules -hierarchy
write -format edif -hierarchy -o module + ".edf" module
write -format db -hierarchy -o module + ".db" module

quit