module rsp_mon(clk,reset_l);
input clk,reset_l;

`define RspPath reality.rcp_0.rsp_0

`ifdef RSP_GATE
`else
`define VUPath `RspPath.vu
`define VR0Path `VUPath.vusl01.vudp0.vdpregfile_i
`define VR1Path `VUPath.vusl01.vudp1.vdpregfile_i
`define VR2Path `VUPath.vusl23.vudp0.vdpregfile_i
`define VR3Path `VUPath.vusl23.vudp1.vdpregfile_i
`define VR4Path `VUPath.vusl45.vudp0.vdpregfile_i
`define VR5Path `VUPath.vusl45.vudp1.vdpregfile_i
`define VR6Path `VUPath.vusl67.vudp0.vdpregfile_i
`define VR7Path `VUPath.vusl67.vudp1.vdpregfile_i
`endif

reg rsp_display_on;

reg [15:0] VCC, VCO;

reg [11:0] pc,su_rd_pc_debug;
reg [31:0] inst_0, inst_1;
reg halt,set_broke,dma_busy;
reg SR_Wen;
reg [31:0] SR_d;
reg [4:0] SR_w_addr;

reg imem_web;
reg [63:0] imem_din;
reg show_imem_on_r1;

reg dmem_we;
reg [15:0] dmem_web;
reg [11:0] dmemh_adr;
reg [11:0] dmeml_adr;
reg [63:0] dmemh_din;
reg [63:0] dmeml_din;

reg [15:0] VUWIen_x;
reg [4:0] vs_waddr_x [0:15];
reg [4:0] vs_waddr_y;
reg [4:0] vs_waddr;
reg VUWIen;
reg [127:0] VS_Data;

reg [15:0] VUWOen_x;
reg [4:0] vv_waddr_x [0:7];
reg [4:0] vv_waddr_y;
reg [4:0] vv_waddr;
reg VUWOen;
reg [127:0] VV_Data;

integer i;

initial 
  begin
    VCC = 0;
    VCO = 0;

    pc = 0;

    su_rd_pc_debug = 0;
    inst_0 = 0;
    inst_1 = 0;
    halt = 0;
    set_broke = 0;
    dma_busy = 0;
    SR_Wen = 0;
    SR_w_addr = 0;
    SR_d = 0;
    imem_web = 1;
    imem_din = 0;
    dmem_we = 1;
    dmem_web = 16'hFFFF;
    dmemh_din = 0;
    dmeml_din = 0;
    show_imem_on_r1 = 0;
    
    VUWIen_x = 0;
    vs_waddr = 0;
    VUWOen_x = 0;
    vv_waddr = 0;
    VS_Data = 0;
    VV_Data = 0;

    rsp_display_on = 0;

    if ($test$plusargs("rsp_mon"))
	rsp_display_on = 1;
    if ($test$plusargs("show_imem_on_r1"))
	show_imem_on_r1 = 1;
  end 

always @(posedge clk)
  if (rsp_display_on) 
      begin
  	pc <= {`RspPath.imem.a,3'b000};
  	inst_0 <= `RspPath.imem.dout[63:32];
  	inst_1 <= `RspPath.imem.dout[31:0];

	imem_web <= `RspPath.imem.web; 
	if (`RspPath.imem.web===1'b0)
	     imem_din <= `RspPath.imem.di; 

	dmem_web <= `RspPath.dmemx2.df_wen_l; 
        dmem_we <= (`RspPath.dmemx2.df_wen_l !==16'hffff);
	if (`RspPath.dmemx2.df_wen_l!==16'hFFFF) begin
	     dmemh_din <= `RspPath.dmemx2.df_datain[127:64];
	     dmeml_din <= `RspPath.dmemx2.df_datain[ 63: 0];
	     dmemh_adr <= { `RspPath.dmemx2.df_addr_high,4'b0 };
	     dmeml_adr <= { `RspPath.dmemx2.df_addr_low,4'b0 };
	end

  	halt <= `RspPath.io_mem_dma.halt;
  	set_broke <= `RspPath.io_mem_dma.set_broke;
  	dma_busy <= `RspPath.io_mem_dma.dma_busy;

        SR_Wen <= `RspPath.su.sudp.suRFile_i.Wen;
	if (`RspPath.su.sudp.suRFile_i.Wen)
         begin
           SR_w_addr <= `RspPath.su.sudp.suRFile_i.w_addr;
           SR_d <= `RspPath.su.sudp.suRFile_i.d;
	 end

`ifdef RSP_GATE
`else
  	su_rd_pc_debug <= `RspPath.su.suctl.issue.su_rd_pc_debug;

	VUWIen_x = 16'h0;
	if (`VR0Path.WIYen) begin VUWIen_x[0] =1; vs_waddr_x[0]  = `VR0Path.wiy_addr; end  
	if (`VR1Path.WIYen) begin VUWIen_x[2] =1; vs_waddr_x[2]  = `VR1Path.wiy_addr; end 
	if (`VR2Path.WIYen) begin VUWIen_x[4] =1; vs_waddr_x[4]  = `VR2Path.wiy_addr; end 
	if (`VR3Path.WIYen) begin VUWIen_x[6] =1; vs_waddr_x[6]  = `VR3Path.wiy_addr; end 
	if (`VR4Path.WIYen) begin VUWIen_x[8] =1; vs_waddr_x[8]  = `VR4Path.wiy_addr; end 
	if (`VR5Path.WIYen) begin VUWIen_x[10]=1; vs_waddr_x[10] = `VR5Path.wiy_addr; end 
	if (`VR6Path.WIYen) begin VUWIen_x[12]=1; vs_waddr_x[12] = `VR6Path.wiy_addr; end 
	if (`VR7Path.WIYen) begin VUWIen_x[14]=1; vs_waddr_x[14] = `VR7Path.wiy_addr; end 

	if (`VR0Path.WIXen) begin VUWIen_x[1] =1; vs_waddr_x[1]  = `VR0Path.wix_addr; end
	if (`VR1Path.WIXen) begin VUWIen_x[3] =1; vs_waddr_x[3]  = `VR1Path.wix_addr; end
	if (`VR2Path.WIXen) begin VUWIen_x[5] =1; vs_waddr_x[5]  = `VR2Path.wix_addr; end
	if (`VR3Path.WIXen) begin VUWIen_x[7] =1; vs_waddr_x[7]  = `VR3Path.wix_addr; end
	if (`VR4Path.WIXen) begin VUWIen_x[9] =1; vs_waddr_x[9]  = `VR4Path.wix_addr; end
	if (`VR5Path.WIXen) begin VUWIen_x[11]=1; vs_waddr_x[11] = `VR5Path.wix_addr; end
	if (`VR6Path.WIXen) begin VUWIen_x[13]=1; vs_waddr_x[13] = `VR6Path.wix_addr; end
	if (`VR7Path.WIXen) begin VUWIen_x[15]=1; vs_waddr_x[15] = `VR7Path.wix_addr; end

        for (i=15; i>=0; i=i-1) if (VUWIen_x[i]) vs_waddr_y =  vs_waddr_x[i];

        VUWIen <= (VUWIen_x!==0);

        vs_waddr <= vs_waddr_y;
	VS_Data = {`VR0Path.mem[vs_waddr_y],`VR1Path.mem[vs_waddr_y],
		   `VR2Path.mem[vs_waddr_y],`VR3Path.mem[vs_waddr_y],
                   `VR4Path.mem[vs_waddr_y],`VR5Path.mem[vs_waddr_y],
		   `VR6Path.mem[vs_waddr_y],`VR7Path.mem[vs_waddr_y]};
  
	VUWOen_x = 8'h0;
	if (`VR0Path.WOen) begin VUWOen_x[0] =1; vv_waddr_x[0] = `VR0Path.wo_addr; end  
	if (`VR1Path.WOen) begin VUWOen_x[1] =1; vv_waddr_x[1] = `VR1Path.wo_addr; end 
	if (`VR2Path.WOen) begin VUWOen_x[2] =1; vv_waddr_x[2] = `VR2Path.wo_addr; end 
	if (`VR3Path.WOen) begin VUWOen_x[3] =1; vv_waddr_x[3] = `VR3Path.wo_addr; end 
	if (`VR4Path.WOen) begin VUWOen_x[4] =1; vv_waddr_x[4] = `VR4Path.wo_addr; end 
	if (`VR5Path.WOen) begin VUWOen_x[5] =1; vv_waddr_x[5] = `VR5Path.wo_addr; end 
	if (`VR6Path.WOen) begin VUWOen_x[6] =1; vv_waddr_x[6] = `VR6Path.wo_addr; end 
	if (`VR7Path.WOen) begin VUWOen_x[7] =1; vv_waddr_x[7] = `VR7Path.wo_addr; end 

        for (i=7; i>=0; i=i-1) if (VUWOen_x[i]) vv_waddr_y =  vv_waddr_x[i];  

        VUWOen <= (VUWOen_x!==0);

        vv_waddr <= vv_waddr_y;
	VV_Data = {`VR0Path.mem[vv_waddr_y],`VR1Path.mem[vv_waddr_y],
		   `VR2Path.mem[vv_waddr_y],`VR3Path.mem[vv_waddr_y],
                   `VR4Path.mem[vv_waddr_y],`VR5Path.mem[vv_waddr_y],
		   `VR6Path.mem[vv_waddr_y],`VR7Path.mem[vv_waddr_y]};

	VCC[0]  <= `VUPath.vusl01.vuctl1.vuctlsl0.vct_cmpcdlo_ac;
	VCC[1]  <= `VUPath.vusl01.vuctl1.vuctlsl1.vct_cmpcdlo_ac;
	VCC[2]  <= `VUPath.vusl23.vuctl1.vuctlsl0.vct_cmpcdlo_ac;
	VCC[3]  <= `VUPath.vusl23.vuctl1.vuctlsl1.vct_cmpcdlo_ac;
	VCC[4]  <= `VUPath.vusl45.vuctl1.vuctlsl0.vct_cmpcdlo_ac;
	VCC[5]  <= `VUPath.vusl45.vuctl1.vuctlsl1.vct_cmpcdlo_ac;
	VCC[6]  <= `VUPath.vusl67.vuctl1.vuctlsl0.vct_cmpcdlo_ac;
	VCC[7]  <= `VUPath.vusl67.vuctl1.vuctlsl1.vct_cmpcdlo_ac;

	VCC[8]  <= `VUPath.vusl01.vuctl1.vuctlsl0.vct_cmpcdhi_ac;
	VCC[9]  <= `VUPath.vusl01.vuctl1.vuctlsl1.vct_cmpcdhi_ac;
	VCC[10] <= `VUPath.vusl23.vuctl1.vuctlsl0.vct_cmpcdhi_ac;
	VCC[11] <= `VUPath.vusl23.vuctl1.vuctlsl1.vct_cmpcdhi_ac;
	VCC[12] <= `VUPath.vusl45.vuctl1.vuctlsl0.vct_cmpcdhi_ac;
	VCC[13] <= `VUPath.vusl45.vuctl1.vuctlsl1.vct_cmpcdhi_ac;
	VCC[14] <= `VUPath.vusl67.vuctl1.vuctlsl0.vct_cmpcdhi_ac;
	VCC[15] <= `VUPath.vusl67.vuctl1.vuctlsl1.vct_cmpcdhi_ac;

	VCO[0]  <= `VUPath.vusl01.vuctl1.vuctlsl0.vct_cryout_ac;
	VCO[1]  <= `VUPath.vusl01.vuctl1.vuctlsl1.vct_cryout_ac;
	VCO[2]  <= `VUPath.vusl23.vuctl1.vuctlsl0.vct_cryout_ac;
	VCO[3]  <= `VUPath.vusl23.vuctl1.vuctlsl1.vct_cryout_ac;
	VCO[4]  <= `VUPath.vusl45.vuctl1.vuctlsl0.vct_cryout_ac;
	VCO[5]  <= `VUPath.vusl45.vuctl1.vuctlsl1.vct_cryout_ac;
	VCO[6]  <= `VUPath.vusl67.vuctl1.vuctlsl0.vct_cryout_ac;
	VCO[7]  <= `VUPath.vusl67.vuctl1.vuctlsl1.vct_cryout_ac;

	VCO[8]  <= `VUPath.vusl01.vuctl1.vuctlsl0.vct_opdneql_ac;
	VCO[9]  <= `VUPath.vusl01.vuctl1.vuctlsl1.vct_opdneql_ac;
	VCO[10] <= `VUPath.vusl23.vuctl1.vuctlsl0.vct_opdneql_ac;
	VCO[11] <= `VUPath.vusl23.vuctl1.vuctlsl1.vct_opdneql_ac;
	VCO[12] <= `VUPath.vusl45.vuctl1.vuctlsl0.vct_opdneql_ac;
	VCO[13] <= `VUPath.vusl45.vuctl1.vuctlsl1.vct_opdneql_ac;
	VCO[14] <= `VUPath.vusl67.vuctl1.vuctlsl0.vct_opdneql_ac;
	VCO[15] <= `VUPath.vusl67.vuctl1.vuctlsl1.vct_opdneql_ac;
`endif
      end

always @(negedge clk)
      begin
	 VUWIen <= 0;
	 VUWOen <= 0;
	 SR_Wen <= 0;
	 imem_web <= 1;
	 dmem_we <= 0;
      end

always @(
         pc 		   or 
         inst_0 	   or 
         inst_1 	   or 
         su_rd_pc_debug    or 
         halt 		   or 
         set_broke 	   or 
         dma_busy	   or
	 posedge SR_Wen	   or 
	 negedge imem_web  or
         posedge dmem_we   or
	 posedge VUWIen	   or
	 posedge VUWOen	   or
	 VCC		   or
	 VCO
        )

  if (rsp_display_on) 
     begin
        $display($time, " : RSP: H=%b B=%b D=%b im=%h (H=%h L=%h) npc=%h, (vcc=%h, vco=%h)",
                halt, set_broke, dma_busy, pc, inst_0, inst_1, su_rd_pc_debug, VCC, VCO);

	if (imem_web===1'b0) 
           $display($time, " : RSP: imem dma write : imem_din= %8h_%8h", 
					imem_din[63:32],imem_din[31:0]);
	if (dmem_web!==16'hFFFF)
	   $display("  dmem write: %2h@%8h %8h_%8h %2h@%8h %8h_%8h",
		dmem_web[15:8],
		dmemh_adr, dmemh_din[63:32], dmemh_din[31:0],
		dmem_web[ 7:0],
		dmeml_adr, dmeml_din[63:32], dmeml_din[31:0]);

	if (SR_Wen)
	   begin
            $display($time, " : RSP: SU Reg: R%0d = %h", SR_w_addr, SR_d);
            if (show_imem_on_r1 && SR_w_addr===5'h1) dump_imem;
	   end

	if (VUWIen)
            $display($time, " : RSP: VU Reg(LS): V%0d = %h", vs_waddr, VS_Data);

	if (VUWOen)
            $display($time, " : RSP: VU Reg(VOP): V%0d = %h", vv_waddr, VV_Data);
     end

task dump_imem;
  reg [9:0] i;
  reg [31:0] dh0,dl0,dh1,dl1;
  begin
    $display("+++++++++++++++++ IMEM DUMP ++++++++++++++++++++++");
    for (i=0; i<512; i=i+2)
      begin
	{ dh0,dl0 } = `RspPath.imem.ram_prim[i  ];
	{ dh1,dl1 } = `RspPath.imem.ram_prim[i+1];
	$display(" IMEM[0x%3h]=%4h_%4h (hex) IMEM[0x%3h]=%4h_%4h (hex)",
		 i,dh0,dl0,i+'h1,dh1,dl1);
      end
  end
endtask

endmodule