`timescale 1ns/1ns

module vclk_regs (vbus_data_reg, vbus_sync_reg, vbus_data, vbus_sync, vclk_in, vclk_out, reset_l);
   input vclk_in, reset_l;
   input  [6:0] vbus_data;
   output [6:0] vbus_data_reg;
   output vclk_out;
   input vbus_sync;
   output vbus_sync_reg;
   reg [6:0] dreg;
   reg sreg;


   buf G1(vclk_out, vclk_in);

   assign #1 vbus_data_reg  = dreg;
   assign #1 vbus_sync_reg  = sreg;

   always @ (posedge vclk_in or negedge reset_l) begin
      if (reset_l)
       begin
         dreg = vbus_data;
         sreg = vbus_sync;
       end
      else
       begin
         dreg = 7'b0;
         sreg = 1'b0;
       end
   end

endmodule