rac.v
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module rac (
RData7, RData6, RData5, RData4, RData3, RData2, RData1, RData0,
SynClk, SynClkFd,
BusEnable, BISTFlag, SCANOut,
BusCtrl, BusData,
BusClk, BDSel, BCSel, BESel, RDSel, RCSel,
Reset,
TData7, TData6, TData5, TData4, TData3, TData2, TData1, TData0,
Vref,
BISTMode, IOSTMode, SCANMode, SCANClk, SCANEn, SCANIn, SynClkIn,
CCtlEn, CCtlLd, CCtlI, CCtlPgm, PwrUp, ExtBE, StopR, StopT,
ByPass, ByPSel, rclkASIC, tclkASIC, PhStall);
output [9:0] RData7, RData6, RData5, RData4, RData3, RData2, RData1, RData0;
output SynClk, SynClkFd;
output BusEnable;
output BISTFlag, SCANOut;
inout BusCtrl;
inout [8:0] BusData;
input BusClk;
input [3:0] BDSel, BCSel, BESel, RDSel, RCSel;
input Reset;
input [10:0] TData7, TData6, TData5, TData4, TData3, TData2, TData1, TData0;
input Vref;
input BISTMode, IOSTMode, SCANMode, SCANClk, SCANEn, SCANIn,SynClkIn;
input CCtlEn, CCtlLd;
input [5:0] CCtlI;
input CCtlPgm, PwrUp, ExtBE, StopR, StopT;
input ByPass, ByPSel, rclkASIC, tclkASIC, PhStall;
rac_near_model #(0, 1, 1, 80, 20) rac_near_model_0 (
RData7, RData6, RData5, RData4, RData3, RData2, RData1, RData0,
SynClk, SynClkFd,
BusEnable, BISTFlag, SCANOut,
BusCtrl, BusData,
BusClk, BDSel, BCSel, BESel, RDSel, RCSel,
Reset,
TData7, TData6, TData5, TData4, TData3, TData2, TData1, TData0,
Vref,
BISTMode, IOSTMode, SCANMode, SCANClk, SCANEn, SCANIn, SynClkIn,
CCtlEn, CCtlLd, CCtlI, CCtlPgm, PwrUp, ExtBE, StopR, StopT,
ByPass, ByPSel, rclkASIC, tclkASIC, PhStall);
endmodule