uPD23C64027.v
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/////////// file name "uPD23C64027.v" ////////////////
// uPD23C64027.v - behavioural model of 64M MASKROM
//
// Copyright 1994, NEC Corporation All Rights Reserved
//
//
// Revision 1.1 94/11/11
`timescale 1 ns / 100ps
/////////// TOP OF TEST CIRCUITS ////////////////
module test_fixture;
wire [15:0] AD;
reg RDB,ALEH,ALEL,CEB;
reg [15:0] io_AD;
assign AD = io_AD;
D23C64027 TOP(AD,
RDB, ALEH, ALEL, CEB);
// ## please enter any additional stimulus from here ##
initial
begin
$timeformat(-9, 0, "ns",10);
$gr_waves("ALEH",ALEH,"ALEL",ALEL,"RDB",RDB,"CEB",CEB,"AD",AD,
"AD_in", io_AD,
"AD_out", TOP.out_buf.AD);
end
// test pattern
initial
begin
CEB=0;
RDB=1;
ALEH=0;
ALEL=0;
#50 ALEH=1; //normal spec read AD=$000000
#50 ALEL=1;
#40 io_AD=16'h0; //{0,0,0,0)<=>(0,0,0,0)}
#30 ALEH=0;
#40 io_AD=16'h0;
#30 ALEL=0;
#4 io_AD=16'h0;
#2000 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
$stop;
#50 ALEH=1; //CEB stand-by
#50 ALEL=1;
#40 CEB=1;
#30 ALEH=0;
#70 ALEL=0;
#2000 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
$stop;
#50 ALEH=1; //tCE read AD=$0001F2
#50 ALEL=1;
#40 CEB=0;io_AD=16'h0; //{0,0,0,0)<=>(0,0,0,0)}
#30 ALEH=0;
#5 io_AD=16'h01f2;
#70 ALEL=0;
// #4 io_AD=16'he67f;
#2000 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
$stop;
#50 ALEH=1; //CSB stand-by AD=$0000FB
#50 ALEL=1;
#40 CEB=0;io_AD=16'h1980; //{(1,1,1,1)<=>(0,0,0,0)}
#30 ALEH=0;
#5 io_AD=16'h01f7;
#70 ALEL=0;
#2000 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
$stop;
#50 ALEH=1; //normal spec read AD=$2FFF80
#50 ALEL=1;
#40 io_AD=16'he67f; //{0,0,0,0)<=>(0,0,0,0)}
#30 ALEH=0;
#40 io_AD=16'hff00;
#30 ALEL=0;
#2000 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
#20 RDB=RDB+1;
#380 RDB=RDB+1;
$stop;
end
// ## please enter any additional stimulus to here ##
endmodule
////////////////////////////////////////////////////////////////////////////
// TOP CELL
////////////////////////////////////////////////////////////////////////////
module D23C64027(
AD, // address in / data out
RDB, // read strobe
ALEH, // address lutch enable H
ALEL, // address lutch enable L
CEB); // chip enable
input RDB,ALEH,ALEL,CEB;
inout [15:0] AD;
wire [15:0] AD;
wire [6:0] row_adrh;
wire [5:0] row_adrl;
wire col_adr;
wire [7:0] col_countadr;
wire RDB,adah,adal,csb,pwd;
wire [15:0] read_data;
/////////////////////////////////////////////
////////////////////////////////////////////////
///// timing speck check //////
////////////////////////////////////////////////
specify
specparam tALES= 70 ;
specparam tALED= 70 ;
specparam tAS = 30 ;
specparam tAH = 5 ;
specparam tCES = 20 ;
specparam tCEH = 5 ;
specparam tL = 2000 ;
specparam tCYC = 400 ;
specparam tR = 20 ;
specparam tRC = 20 ;
specparam tS = 0 ;
// timing check //
$setup(posedge ALEL, negedge ALEH, tALES);
$setup(negedge ALEH, negedge ALEL, tALED);
$setup(AD , negedge ALEH, tAS);
$hold (negedge ALEH, AD , tAH);
$setup(AD , negedge ALEL, tAS);
$hold (negedge ALEL, AD , tAH);
$setup(CEB , negedge ALEH, tCES);
$hold (negedge ALEH, CEB , tCEH);
$setup(posedge RDB , posedge ALEH, tRC);
$setup(negedge ALEL, negedge RDB , tL);
$setup(posedge ALEH, posedge ALEL, tS);
$period(negedge RDB, tCYC);
$width (posedge RDB, tR);
endspecify
/////////////////////////////////////////////
uProg_add_dec pad (csb, //PROGRAMABLE ADRESS DECODER
AD[15:0], adah);
uController ctl (adah ,adal, pwd, clk1, //INTERNAL CONTROLL CLOCK
CEB, ALEH, ALEL, csb, RDB);
uCell cell (read_data, //MEMORY CELL
row_adrh, row_adrl,col_adr, col_countadr, pwd);
uRow_register row_reg(row_adrh, row_adrl, //ROW ADDRESS REGISTER
AD[15:0], adah, adal);
uCol_register col_reg(col_adr, col_countadr, //COLUMN ADDRESS REGISTER
AD[15:0], adal, clk1); // & COUNTER
uOut_buffer out_buf(AD[15:0], //OUTPUT BUFFER
read_data, clk1);
endmodule
////////////////////////////////////////////////////////////////////////////
// PROGRAMABLE ADDRESS DECODER
////////////////////////////////////////////////////////////////////////////
module uProg_add_dec(csb,
AD, adah);
//////////mask program address///////////////
parameter pra7 = 0, // mask program address AD7(H)
pra8 = 0, // mask program address AD8(H)
pra11 = 0, // mask program address AD11(H)
pra12 = 0; // mask program address AD12(H)
/////////////////////////////////////////////
input [15:0] AD;
input adah;
output csb;
reg csb,a7,a8,a11,a12;
reg [15:0] ad;
always @({AD,adah})
begin
ad = AD;
if (adah == 1)
begin
a7 = ad[7];
a8 = ad[8];
a11 = ad[11];
a12 = ad[12];
if({pra7,pra8,pra11,pra12} == {a7,a8,a11,a12}) csb = 0;
else csb=1;
end
end
endmodule
////////////////////////////////////////////////////////////////////////////
// INTERNAL CONTROLL CLOCK
////////////////////////////////////////////////////////////////////////////
module uController(adah, adal, pwd, clk1,
CEB, ALEH, ALEL, csb, RDB);
input CEB,ALEH,ALEL,csb,RDB;
output adah,adal,pwd,clk1;
reg adah,adal,pwd,clk1;
always @({ALEH,ALEL})
begin
#5 adah = ALEH & ALEL;
adal = (!ALEH) & ALEL;
end
always @({ALEH,ALEL,CEB,csb})
pwd = ALEH|ALEL|CEB|csb;
always @({RDB,pwd})
clk1 = RDB|pwd;
endmodule
////////////////////////////////////////////////////////////////////////////
// MEMORY CELL
////////////////////////////////////////////////////////////////////////////
module uCell(read_data,
row_adrh, row_adrl, col_adr, col_countadr, pwd);
input [6:0] row_adrh;
input [5:0] row_adrl;
input col_adr;
input [7:0] col_countadr;
input pwd;
output [15:0] read_data;
reg [15:0] DATA[0:4194303]; // memory cell
reg [15:0] read_data;
always @({row_adrh,row_adrl,col_adr,col_countadr,pwd}) // data read
begin
if(pwd==0)
begin
//////////momory cell data write/////////////
DATA[{row_adrh,row_adrl,col_adr,col_countadr}]={row_adrh,row_adrl,col_adr, col_countadr};
/////////////////////////////////////////////
read_data=DATA[{row_adrh,row_adrl,col_adr,col_countadr}];
end
end
endmodule
////////////////////////////////////////////////////////////////////////////
// ROW ADDRESS REGISTER
////////////////////////////////////////////////////////////////////////////
module uRow_register(row_adrh, row_adrl,
AD, adah, adal);
input adah;
input adal;
input [15:0] AD;
output [6:0] row_adrh;
output [5:0] row_adrl;
reg [6:0] row_adrh;
reg [5:0] row_adrl;
reg [15:0] ad;
always @({AD,adah,adal})
begin
ad = AD;
begin
if (adah == 1) row_adrh[6:0] = AD[6:0];
if (adal == 1) row_adrl[5:0] = AD[15:10];
end
end
endmodule
////////////////////////////////////////////////////////////////////////////
// COLUMN ADDRESS REGISTER & COUNTER
////////////////////////////////////////////////////////////////////////////
module uCol_register(col_adr, col_countadr,
AD, adal, clk1);
input clk1,adal;
input [15:0] AD;
output col_adr;
output [7:0] col_countadr;
reg col_adr;
reg [7:0] col_countadr;
reg [15:0] ad;
always @({AD,adal})
begin
ad = AD;
if (adal == 1)
begin
col_countadr[7:0] = AD[8:1];
col_adr = AD[9];
end
end
always @(negedge clk1)
begin
col_countadr[7:0] = col_countadr[7:0]+'h1 ;
end
endmodule
////////////////////////////////////////////////////////////////////////////
// OUTPUT BUFFER
////////////////////////////////////////////////////////////////////////////
module uOut_buffer (AD,
read_data, clk1);
input clk1;
input [15:0] read_data;
output [15:0] AD;
wire [15:0] read_data;
reg [15:0] AD;
parameter tRD = 150; // tRD speck
parameter tDF = 60; // tDF speck
parameter tOH = 0; // tOH speck
always @(clk1)
if(clk1==1) AD = #(tDF) 16'hz;
always @(negedge clk1)
AD = #(tRD) read_data;
endmodule
/////////// END OF FILE ////////////////