`timescale 1ns/1ns

module GCB_JK (q, qn, j, k, cp, sdn, cdn);
input j, k, cp, sdn, cdn;
output q, qn;

reg q, qn;
wire next_q;

always @(sdn or cdn) begin
	case ({sdn, cdn})
		2'b00 : begin
			assign q = 0;
			assign qn = 0;
			end

		2'b01 : begin
			assign q = 1;
			assign qn = 0;
			end

		2'b10 : begin
			assign q = 0;
			assign qn = 1;
			end

		2'b11 : begin
			deassign q;
			deassign qn;
			end
		endcase
	end

jk_prim jk_next(next_q, j, k, q);

always @(posedge cp) begin
	q <= #1 next_q;
	qn <= #1 ~next_q;
	end
endmodule


primitive jk_prim(out, j, k, q);
output out;
input j, k, q;

table
        ?  0  1  : 1;
        1  ?  0  : 1;
        ?  1  1  : 0;
        0  ?  0  : 0;
        1  0  ?  : 1;
        0  1  ?  : 0;
	endtable
endprimitive