module = csfiforptr

/* set up a new search path */
search_path = search_path + "../../inc"


/* read the verilog sources */

read -f verilog ../src/csfiforptr.v

current_design = csfiforptr

/* compile restrictions
set_dont_touch { ne35hd130d/nt01d* }
set_dont_use { ne35hd130d/mbnfnq ne35hd130d/mbnfnr }
set_dont_use { ne35hd130d/jk* } */

/* setup operating conditions */

set_operating_conditions NOM
set_wire_load 256000 -mode top
standard_load = 0.01

link 

check_design > csfiforptr.lint

/* timing/area constraints */

/* inputs */
create_clock gclk -period 14.0 -waveform {7.0 14.0}
set_max_transition 0.8 current_design
set_input_delay 13.0 -clock gclk {update_rptr}
set_input_delay 12.0 -clock gclk {one_word_cmd}
set_input_delay 2.0 -clock gclk {cmd_size}
set_driving_cell -cell or03d2 {one_word_cmd}
set_driving_cell -cell ao05d2 {update_rptr}
set_driving_cell -cell dfntnb {cmd_size[*]}
/* outputs */
set_output_delay 13.0 -clock gclk {read_adrs}
set_output_delay 13.0 -clock gclk {base_adrs}
set_load 0.20 {base_adrs[*]}
set_load 0.05 {read_adrs[*]}

/* compile */

compile -map_effort high -ungroup_all

report -reference

report_constraint -all_violators

write -f edif -o csfiforptr.edf -hier csfiforptr

quit