/************************************************************************\
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 \************************************************************************/

// $Id: io_mem_dma.v,v 1.1.1.1 2002/05/17 06:14:57 blythe Exp $


module io_mem_dma(clock, reset_l,
   cp0_enable, cbus_read_enable, cbus_write_enable, cbus_select, cbus_command,
   dma_start, dma_last, dma_grant, read_grant, cp0_cmd_select, cp0_address,
   cp0_read, cp0_write, set_broke, cmd_read, cmd_address, bist_done, bist_fail,
   dma_request, reg_read_request, mem_read_request, imem_select, mem_address,
   mem_read, mem_write, mem_mask, halt, single_step, dma_busy, cmd_ready,
   pc_write, pc_data, io_read_select, io_write_select, mem_load, io_load,
   interrupt, bist_go, bist_check,
	cp0_data, cbus_data);

`include "sp.vh"

input clock;											// system clock
input reset_l;											// system reset_l

input cp0_enable;										// enable cp0 tristate drivers
input cbus_read_enable;								// enable cbus read mux
input cbus_write_enable;							// enable cbus tristate drivers
input [CBUS_SELECT_SIZE-1:0] cbus_select;		// cbus data select
input [CBUS_COMMAND_SIZE-1:0] cbus_command;	// cbus data type
input dma_start;										// dbus DMA data start
input dma_last;										// dbus DMA data end
input dma_grant;										// SP DMA request granted
input read_grant;										// SP read request granted
input cp0_cmd_select;								// sp selected
input [SP_REG_ADDRESS_SIZE-1:0] cp0_address;	// DMA register address
input cp0_read;										// enable register read
input cp0_write;										// enable register write
input set_broke;										// status from RSP
input cmd_read;										// DP DMEM read request
input [SP_MEM_ADDRESS_SIZE-1:0] cmd_address;	// DP DMEM read address
input bist_done;										// IMEM BIST done (pulse)
input [SP_BIST_FAIL_SIZE-1:0] bist_fail;		// IMEM BIST fail (pulse)

output dma_request;									// sp DMA request
output reg_read_request;							// reg read request
output mem_read_request;							// dmem/imem read request
output imem_select;									// enable IMEM read/write
output [SP_MEM_ADDRESS_SIZE-1:0] mem_address; // DMEM/IMEM address
output mem_read;										// read DMA in progress
output mem_write;										// write DMA in progress
output [SP_MEM_MASK_SIZE-1:0] mem_mask;		// DMA read/write byte mask
output halt;											// status to RSP
output single_step;									// status to RSP
output dma_busy;										// status to RSP
output cmd_ready;										// DP CMDBUF read ready
output pc_write;										// program counter write enable
output [SP_PC_SIZE-1:0] pc_data;					// program counter write data bus
output io_read_select;								// select high/low data
output io_write_select;								// select IO write data
output mem_load;										// load cbus reg from imem/dmem
output io_load;										// load cbus reg from cbus
output interrupt;										// rsp generated interrupt
output bist_go;										// start IMEM BIST
output bist_check;									// BIST BIST

inout [CP0_DATA_SIZE-1:0] cp0_data;				// CP0 data bus
inout [CBUS_DATA_SIZE-1:0] cbus_data;			// IO data bus

mem_dma mem_dma(clock, reset_l,
   cp0_enable, cbus_read_enable, cbus_write_enable, cbus_select, cbus_command,
   dma_start, dma_last, dma_grant, read_grant, cp0_cmd_select, cp0_address,
   cp0_read, cp0_write, set_broke, cmd_read, cmd_address, bist_done, bist_fail,
   dma_request, reg_read_request, mem_read_request, imem_select, mem_address,
   mem_read, mem_write, mem_mask, halt, single_step, dma_busy, cmd_ready,
   pc_write, pc_data, io_read_select, io_write_select, mem_load, io_load,
   interrupt, bist_go, bist_check,
	cp0_data, cp0_data, cbus_data, cbus_data);

endmodule

module mem_dma(clock, reset_l,
   cp0_enable, cbus_read_enable, cbus_write_enable, cbus_select, cbus_command,
   dma_start, dma_last, dma_grant, read_grant, cp0_cmd_select, cp0_address,
   cp0_read, cp0_write, set_broke, cmd_read, cmd_address, bist_done, bist_fail,
   dma_request, reg_read_request, mem_read_request, imem_select, mem_address,
   mem_read, mem_write, mem_mask, halt, single_step, dma_busy, cmd_ready,
   pc_write, pc_data, io_read_select, io_write_select, mem_load, io_load,
   interrupt, bist_go, bist_check, cp0_data_in, cp0_data, cbus_data_in, cbus_data);

`include "sp.vh"

input clock;											// system clock
input reset_l;											// system reset_l

input cp0_enable;										// enable cp0 tristate drivers
input cbus_read_enable;								// enable cbus read mux
input cbus_write_enable;							// enable cbus tristate drivers
input [CBUS_SELECT_SIZE-1:0] cbus_select;		// cbus data select
input [CBUS_COMMAND_SIZE-1:0] cbus_command;	// cbus data type
input dma_start;										// dbus DMA data start
input dma_last;										// dbus DMA data end
input dma_grant;										// SP DMA request granted
input read_grant;										// SP read request granted
input cp0_cmd_select;								// sp selected
input [SP_REG_ADDRESS_SIZE-1:0] cp0_address;	// DMA register address
input cp0_read;										// enable register read
input cp0_write;										// enable register write
input set_broke;										// status from RSP
input cmd_read;										// DP DMEM read request
input [SP_MEM_ADDRESS_SIZE-1:0] cmd_address;	// DP DMEM read address
input bist_done;										// IMEM BIST done (pulse)
input [SP_BIST_FAIL_SIZE-1:0] bist_fail;		// IMEM BIST fail (pulse)

output dma_request;									// sp DMA request
output reg_read_request;							// reg read request
output mem_read_request;							// dmem/imem read request
output imem_select;									// enable IMEM read/write
output [SP_MEM_ADDRESS_SIZE-1:0] mem_address; // DMEM/IMEM address
output mem_read;										// read DMA in progress
output mem_write;										// write DMA in progress
output [SP_MEM_MASK_SIZE-1:0] mem_mask;		// DMA read/write byte mask
output halt;											// status to RSP
output single_step;									// status to RSP
output dma_busy;										// status to RSP
output cmd_ready;										// DP CMDBUF read ready
output pc_write;										// program counter write enable
output [SP_PC_SIZE-1:0] pc_data;					// program counter write data bus
output io_read_select;								// select high/low data
output io_write_select;								// select IO write data
output mem_load;										// load cbus reg from imem/dmem
output io_load;										// load cbus reg from cbus
output interrupt;										// rsp generated interrupt
output bist_go;										// start IMEM BIST
output bist_check;									// BIST BIST

input [CP0_DATA_SIZE-1:0] cp0_data_in;				// CP0 data bus
output [CP0_DATA_SIZE-1:0] cp0_data;				// CP0 data bus
input [CBUS_DATA_SIZE-1:0] cbus_data_in;			// IO data bus
output [CBUS_DATA_SIZE-1:0] cbus_data;			// IO data bus


// input/output registers
reg dma_request;
reg reg_read_request;
reg mem_read_request;
reg imem_select;
reg [SP_DMA_MASTER_ADDRESS_SIZE-1:0] mem_address;
reg mem_read;
reg mem_write;
reg [SP_MEM_MASK_SIZE-1:0] mem_mask;
reg halt;
reg single_step;
reg dma_busy;
reg pc_write;
reg io_read_select;
reg io_write_select;
reg mem_load;
reg interrupt;
reg [CBUS_COMMAND_SIZE-1:0] cbus_command_reg;
reg [CBUS_DATA_SIZE-1:0] cbus_data_reg;

// output pseudo registers
reg [CP0_DATA_SIZE-1:0] cp0_data_out;

// SP access registers
reg master_imem_select;
reg [SP_DMA_MASTER_ADDRESS_SIZE-1:0] master_address;
reg [SP_DMA_SLAVE_ADDRESS_SIZE-1:0] slave_address;
reg [SP_DMA_SKIP_SIZE-1:0] skip;
reg [SP_DMA_COUNT_SIZE-1:0] count;
reg [SP_DMA_LENGTH_SIZE-1:0] length;
reg read;
reg [SP_MEM_ADDRESS_SIZE+1:0] io_read_address;
reg [SP_MEM_ADDRESS_SIZE+1:0] io_write_address;
reg reg_select;
reg dma_full;
reg io_read_full;
reg io_write_full;
reg broke;
reg interrupt_on_break;

// request registers
reg [SP_DMA_MASTER_ADDRESS_SIZE-1:0] master_address_sum;
reg [SP_DMA_SLAVE_ADDRESS_SIZE-1:0] slave_address_sum;
reg [SP_DMA_LENGTH_SIZE-1:0] length_sum;
reg [SP_DMA_COUNT_SIZE-1:0] count_sum;
reg [SP_DMA_SKIP_SIZE-1:0] skip_pl;
reg [SP_DMA_LENGTH_SIZE-1:0] length_pl;
reg read_pl;
reg [DMA_LENGTH_SIZE-1:0] transfer_length;
reg imem_select_pl;
reg dma_imem_select_pl;
reg [SP_DMA_MASTER_ADDRESS_SIZE-1:0] dma_mem_address_pl;
reg dma_read_pl;
reg dma_valid;
reg io_valid;
reg cpu_semaphore_read;
reg cpu_semaphore_write;
reg cpu_semaphore;
reg semaphore;

// dma registers
reg [SP_DMA_MASTER_ADDRESS_SIZE-1:0] mem_address_sum;
reg mem_busy;

// bist and signal registers
reg bist_go;
reg bist_check;
reg bist_done_reg;
reg [SP_BIST_FAIL_SIZE-1:0] bist_fail_reg;
reg [SP_SIGNAL_SIZE-1:0] signal;

// bus state machine
reg [1:0] bus_state;
parameter
   STATE_BUS_IDLE			= 0,
   STATE_BUS_REG_WRITE	= 1,
   STATE_BUS_REG_READ	= 2,
   STATE_BUS_MEM_READ	= 3;


// request state machine
reg [1:0] request_state;
parameter
   STATE_REQUEST_IDLE	= 0,
   STATE_REQUEST_IO		= 1,
   STATE_REQUEST_DMA		= 2,
   STATE_REQUEST_NEXT	= 3;


// DMA state machine
reg [2:0] dma_state;
parameter
   STATE_DMA_IDLE				= 0,
   STATE_WRITE_PRIMARY		= 1,
   STATE_WRITE_SECONDARY	= 2,
   STATE_READ_PRIMARY		= 3,
   STATE_READ_SECONDARY		= 4;


// CMD state machine
reg cmd_state;
parameter
   STATE_CMD_PRIMARY		= 0,
   STATE_CMD_SECONDARY	= 1;


// IO state machine
reg[2:0] io_state;
parameter
   STATE_IO_IDLE				= 0,
   STATE_IO_READ_1			= 1,
   STATE_IO_READ_2			= 2,
   STATE_IO_READ_3			= 3,
   STATE_IO_IMEM_WRITE_1	= 4,
   STATE_IO_IMEM_WRITE_2	= 5,
   STATE_IO_IMEM_WRITE_3	= 6,
   STATE_IO_WRITE				= 7;

// cbus tristate drivers
wire mem_cp0_enable = cp0_enable & ~cp0_cmd_select;
cp0_driver cp0_driver_0(cp0_data_out, mem_cp0_enable, cp0_data);
cbus_driver cbus_driver_0(cbus_data_reg, cbus_write_enable, cbus_data);

// Program counter write data
assign pc_data = cbus_data_reg >> SP_PC_OFFSET;

// DP CMDBUF DMA ready logic
assign cmd_ready = ~io_valid & ~mem_busy;

// IO select logic
wire [SP_MEM_ADDRESS_SIZE+1:0] next_io_address;
wire [BUS_ID_SIZE-1:0] next_id_select;
wire [SP_DEVICE_SIZE-1:0] next_device_select;
wire next_sp_select;
wire next_mem_select;
wire next_cp0_select;
wire next_reg_select;
wire next_write_command;
wire next_read_command;
assign next_io_address = cbus_data_reg >> IO_OFFSET_SIZE;
assign next_id_select = cbus_data_reg >> BUS_ID_OFFSET;
assign next_device_select = cbus_data_reg >> SP_DEVICE_OFFSET;
assign next_sp_select = next_id_select == BUS_ID_SP;
assign next_mem_select = next_device_select == SP_DEVICE_MEM;
assign next_cp0_select = next_device_select == SP_DEVICE_CP0;
assign next_reg_select = next_device_select == SP_DEVICE_REG;
assign next_write_command
  = (cbus_command_reg == CBUS_WRITE_COMMAND) && next_sp_select;
assign next_read_command
  = (cbus_command_reg == CBUS_READ_COMMAND) && next_sp_select;

assign io_load = next_write_command && next_mem_select;

wire [CBUS_DATA_SIZE-1:0] read_status;
assign read_status = {signal, interrupt_on_break, single_step,
  io_write_full, dma_full, dma_busy, broke, halt};

// DMA register read
always @(cp0_address or imem_select_pl or master_address_sum
 or slave_address_sum or skip_pl or count_sum or length_sum
 or read_status or dma_full or dma_busy or semaphore or cpu_semaphore_write)
	case (cp0_address)
		SP_DMA_MASTER_ADDRESS :
		  cp0_data_out = {imem_select_pl, master_address_sum, 3'b0};
		SP_DMA_SLAVE_ADDRESS :
		  cp0_data_out = {slave_address_sum, 3'b0};
		SP_DMA_READ_LENGTH, SP_DMA_WRITE_LENGTH :
		   cp0_data_out = {skip_pl, 3'b0, count_sum, length_sum, 3'b0};
		SP_DMA_STATUS :
			cp0_data_out = read_status;
		SP_DMA_FULL :
			cp0_data_out = dma_full;
		SP_DMA_BUSY :
			cp0_data_out = dma_busy;
		SP_DMA_SEMAPHORE :
			cp0_data_out = semaphore && !cpu_semaphore_write;
		default :
		   cp0_data_out = 'bx;
		endcase


always @(posedge clock) begin : cbus_block
	reg [DMA_ADDRESS_SIZE-1:0] address;
	reg [DMA_LENGTH_SIZE-1:0] length;
	reg [DMA_DELAY_SIZE-1:0] delay;
	reg [CBUS_DATA_SIZE-1:0] cbus_data_out;

	address = {slave_address_sum, 3'b000};
	length = {transfer_length, 3'b111};
	delay = read_pl ? 2 : -5;

	case (cbus_select)
		CBUS_ADDRESS_SELECT :
		  cbus_data_out = address;
		CBUS_LENGTH_SELECT :
		  cbus_data_out = {BUS_DEVICE_SP, delay, read_pl, length};
		CBUS_DATA_SELECT :
			if (reg_select) case (io_read_address[SP_REG_ADDRESS_SIZE-1:0])
				SP_REG_PC :
				  cbus_data_out = cp0_data_in[SP_PC_SIZE-1:0] << SP_PC_OFFSET;
				SP_REG_BIST :
				  cbus_data_out
				  = {bist_fail_reg, bist_done_reg, bist_go, bist_check};
				default :
				   cbus_data_out = 'bx;
				endcase
			else case (io_read_address[SP_REG_ADDRESS_SIZE-1:0])
				SP_DMA_MASTER_ADDRESS :
				  cbus_data_out = {imem_select_pl, master_address_sum, 3'b0};
				SP_DMA_SLAVE_ADDRESS :
				  cbus_data_out = {slave_address_sum, 3'b0};
				SP_DMA_READ_LENGTH, SP_DMA_WRITE_LENGTH :
				  cbus_data_out = {skip_pl, 3'b0, count_sum, length_sum, 3'b0};
				SP_DMA_STATUS :
				  cbus_data_out = read_status;
				SP_DMA_FULL :
					cbus_data_out = dma_full;
				SP_DMA_BUSY :
					cbus_data_out = dma_busy;
				SP_DMA_SEMAPHORE :
					cbus_data_out = cpu_semaphore;
				default :
				   cbus_data_out = 'bx;
				endcase
		default :
		  cbus_data_out = 'bx;
		endcase

	cbus_command_reg <= cbus_command;
	cbus_data_reg <= cbus_read_enable ? cbus_data_in : cbus_data_out;
	end


always @(posedge clock or negedge reset_l) begin
	if (!reset_l) begin
		// resetable registers
		dma_request <= LOW;
		reg_read_request <= LOW;
		mem_read_request <= LOW;
		mem_read <= LOW;
		mem_write <= LOW;
		mem_mask <= 0;
		halt <= HIGH;
		single_step <= LOW;
		dma_busy <= LOW;
		pc_write <= LOW;
		mem_load <= LOW;
		interrupt <= LOW;
		dma_full <= LOW;
		io_read_full <= LOW;
		io_write_full <= LOW;
		broke <= LOW;
		interrupt_on_break <= LOW;
		dma_valid <= LOW;
		io_valid <= LOW;
		mem_busy <= LOW;
		bist_go <= LOW;
		bist_check <= LOW;
		master_imem_select <= 0;
		master_address <= 0;
		slave_address <= 0;
		skip <= 0;
		count <= 0;
		length <= 0;
		read <= LOW;
		signal <= 0;

		bus_state <= STATE_BUS_IDLE;
		request_state <= STATE_REQUEST_IDLE;
		dma_state <= STATE_DMA_IDLE;
		cmd_state <= STATE_CMD_PRIMARY;
		io_state <= STATE_IO_IDLE;

		imem_select <= 0;
		mem_address <= 0;
		io_read_select <= LOW;
		io_write_select <= LOW;
		io_read_address <= 0;
		io_write_address <= 0;
		reg_select <= LOW;
		master_address_sum <= 0;
		slave_address_sum <= 0;
		length_sum <= 0;
		count_sum <= 0;
		skip_pl <= 0;
		length_pl <= 0;
		read_pl <= LOW;
		transfer_length <= 0;
		imem_select_pl <= 0;
		dma_imem_select_pl <= 0;
		dma_mem_address_pl <= 0;
		dma_read_pl <= LOW;
		mem_address_sum <= 0;
		bist_done_reg <= LOW;
		bist_fail_reg <= 0;
		cpu_semaphore_read <= LOW;
		cpu_semaphore_write <= LOW;
		cpu_semaphore <= LOW;
		semaphore <= LOW;
		end
	else begin : main_block
		reg [SP_REG_ADDRESS_SIZE-1:0] reg_address;
		reg [SP_REG_DATA_SIZE-1:0] reg_data;
		reg dma_reg_write;
		reg io_status_reg_write;
		reg cp0_status_reg_write;
		reg [SP_MEM_MASK_SIZE-1:0] next_mem_mask;
		reg next_pc_write;
		reg next_mem_write;
		reg next_mem_read;
		reg set_interrupt;
		reg clear_interrupt;
		reg set_single_step;
		reg clear_single_step;
		reg clear_broke;
		reg set_halt;
		reg clear_halt;
		reg set_interrupt_on_break;
		reg clear_interrupt_on_break;
		reg [SP_SIGNAL_SIZE-1:0] set_signal;
		reg [SP_SIGNAL_SIZE-1:0] clear_signal;
		reg next_reg_read_request;
		reg next_mem_read_request;
		reg next_mem_load;
		reg next_mem_busy;
		reg next_cpu_semaphore_read;
		reg next_cpu_semaphore_write;
		reg load_io_mem_address;
		reg load_dma_mem_address;
		reg load_count;
		reg decrement_count;
		reg [7:0] max_page;
		reg [SP_DMA_SLAVE_ADDRESS_SIZE-1:0] slave_address_adder0;
		reg [SP_DMA_SLAVE_ADDRESS_SIZE-1:0] slave_address_adder1;
		reg slave_address_adder2;
		reg [SP_DMA_MASTER_ADDRESS_SIZE-1:0] master_address_adder0;
		reg [SP_DMA_MASTER_ADDRESS_SIZE-1:0] master_address_adder1;
		reg [SP_DMA_LENGTH_SIZE-1:0] length_adder0;
		reg [SP_DMA_LENGTH_SIZE-1:0] length_adder1;
		reg next_dma_full;
		reg next_dma_busy;
		reg next_io_imem_select;
		reg [SP_MEM_ADDRESS_SIZE-1:0] next_io_mem_address;
		reg next_io_word_select;
		reg next_bist_done;
		reg [SP_BIST_FAIL_SIZE-1:0] next_bist_fail;
		reg cp0_semaphore_select;
		reg cp0_semaphore_read;
		reg cp0_semaphore_write;

		next_mem_mask = 0;
		next_pc_write = LOW;
		next_mem_write = LOW;
		next_mem_read = LOW;
		next_reg_read_request = LOW;
		next_mem_read_request = LOW;
		next_mem_load = LOW;
		next_mem_busy = LOW;
		next_dma_full = dma_full;
		next_dma_busy = LOW;
		next_cpu_semaphore_read = LOW;
		next_cpu_semaphore_write = LOW;
		load_io_mem_address = LOW;
		load_dma_mem_address = LOW;
		load_count = LOW;
		decrement_count = LOW;
		set_interrupt = LOW;
		clear_interrupt = LOW;
		set_single_step = LOW;
		clear_single_step = LOW;
		clear_broke = LOW;
		set_halt = LOW;
		clear_halt = LOW;
		set_interrupt_on_break = LOW;
		clear_interrupt_on_break = LOW;
		set_signal = 0;
		clear_signal = 0;

		slave_address_adder0 = slave_address_sum;
		slave_address_adder1 = 0;
		slave_address_adder2 = LOW;
		master_address_adder0 = master_address_sum;
		master_address_adder1 = -1;
		length_adder0 = length_sum;
		length_adder1 = -1;

		{next_io_imem_select, next_io_mem_address, next_io_word_select} =
		  io_write_full ? io_write_address : io_read_address;

		reg_address = cp0_address;
		reg_data = cp0_data_in;
		dma_reg_write = LOW;
		io_status_reg_write = LOW;
		cp0_status_reg_write = LOW;

		// bist pulse capture
		next_bist_done = bist_done_reg | bist_done;
		next_bist_fail = bist_fail_reg | bist_fail;

		// semaphore control
		cp0_semaphore_select = cp0_address == SP_DMA_SEMAPHORE;
		cp0_semaphore_read = cp0_read && cp0_semaphore_select;
		cp0_semaphore_write = cp0_write && cp0_semaphore_select;

		if (cp0_write && !cp0_cmd_select) begin
			if (cp0_address[SP_REG_ADDRESS_SIZE-1:0] == SP_DMA_STATUS) begin
				cp0_status_reg_write = HIGH;
				end
			else begin
				dma_reg_write = HIGH;
				end
			end

		// CBUS read/write
		case (bus_state)
			STATE_BUS_IDLE : begin
				if (next_write_command) begin
					// IO write

					io_write_address <= next_io_address;
					reg_select <= next_reg_select;

					case (HIGH) // synopsys parallel_case
						next_mem_select : begin
							if (io_write_full) begin
								$display("Panic!  MEM write register overflow");
								$finish;
								end
							else begin
								io_write_full <= HIGH;
								end
							bus_state <= STATE_BUS_IDLE;
							end

						next_cp0_select : begin
							bus_state <= STATE_BUS_REG_WRITE;
							end

						next_reg_select : begin
							next_pc_write =
							  next_io_address[SP_REG_ADDRESS_SIZE-1:0] == SP_REG_PC;
							bus_state <= STATE_BUS_REG_WRITE;
							end

						default : begin
							bus_state <= STATE_BUS_IDLE;
							end
						endcase
					end
				else if (next_read_command) begin
					// IO read

					io_read_address <= next_io_address;
					reg_select <= next_reg_select;

					case (HIGH) // synopsys parallel_case
						next_mem_select : begin
							if (io_read_full) begin
								$display("Panic!  MEM read register overflow");
								$finish;
								end
							else begin
								io_read_full <= HIGH;
								end
							bus_state <= STATE_BUS_MEM_READ;
							end

						next_cp0_select : begin
							next_cpu_semaphore_read =
							  next_io_address[SP_REG_ADDRESS_SIZE-1:0]
							  == SP_DMA_SEMAPHORE;
							next_reg_read_request = HIGH;
							bus_state <= STATE_BUS_REG_READ;
								end

						next_reg_select : begin
							next_reg_read_request = HIGH;
							bus_state <= STATE_BUS_REG_READ;
							end

						default : begin
							bus_state <= STATE_BUS_IDLE;
							end
						endcase
					end
				else begin
					bus_state <= STATE_BUS_IDLE;
					end
				end

			STATE_BUS_REG_WRITE : begin
				if (reg_select) begin
					if (io_write_address[SP_REG_ADDRESS_SIZE-1:0] == SP_REG_BIST)
					  begin : bist_block
						reg next_bist_go;
						reg next_bist_check;
						reg clear_bist;

						{clear_bist, next_bist_go, next_bist_check} = cbus_data_reg;

						bist_go <= next_bist_go;
						bist_check <= next_bist_check;

						if (clear_bist) begin
							next_bist_done = LOW;
							next_bist_fail = 0;
							end
						end
					end
				else begin
					case (io_write_address[SP_REG_ADDRESS_SIZE-1:0])
						SP_DMA_STATUS : begin
							io_status_reg_write = HIGH;
							end
						SP_DMA_SEMAPHORE : begin
							next_cpu_semaphore_write = HIGH;
							end
						SP_DMA_MASTER_ADDRESS, SP_DMA_SLAVE_ADDRESS,
						SP_DMA_READ_LENGTH, SP_DMA_WRITE_LENGTH : begin
							reg_address = io_write_address;
							reg_data = cbus_data_reg;
							dma_reg_write = HIGH;
							end
						endcase
					end
				bus_state <= STATE_BUS_IDLE;
				end

			STATE_BUS_REG_READ : begin
				if (read_grant) begin
					bus_state <= STATE_BUS_IDLE;
					end
				else begin
					next_reg_read_request = HIGH;
					bus_state <= STATE_BUS_REG_READ;
					end
				end

			STATE_BUS_MEM_READ : begin
				if (io_read_full) begin
					// wait for read data
					bus_state <= STATE_BUS_MEM_READ;
					end
				else if (read_grant) begin
					// read is complete
					bus_state <= STATE_BUS_IDLE;
					end
				else begin
					// begin or continue IO read request
					next_mem_read_request = HIGH;
					bus_state <= STATE_BUS_MEM_READ;
					end
				end

			default : begin
				bus_state <= 'bx;
				end
			endcase

		if (dma_reg_write) begin
			// write to a DMA register
			case (reg_address)
				SP_DMA_MASTER_ADDRESS : begin
					if (dma_full) begin
						// set error bit
						$display("Panic!  DMA register double buffer overflow");
						$finish;
						end
					else begin
						// write the SP master address register
						{master_imem_select, master_address}
						  <= reg_data >> DMA_OFFSET_SIZE;
						end
					end

				SP_DMA_SLAVE_ADDRESS : begin
					if (dma_full) begin
						// set error bit
						$display("Panic!  DMA register double buffer overflow");
						$finish;
						end
					else begin
						// write the RDRAM slave address register
						slave_address <= reg_data >> DMA_OFFSET_SIZE;
						end
					end

				SP_DMA_READ_LENGTH : begin
					if (dma_full) begin
						// set error bit
						$display("Panic!  DMA register double buffer overflow");
						$finish;
						end
					else begin
						// write skip, length, and count register
						// and begin a DMA read
						next_dma_full = HIGH;
						length <= reg_data >> DMA_OFFSET_SIZE;
						count <= reg_data
						  >> (DMA_OFFSET_SIZE + SP_DMA_LENGTH_SIZE);
						skip <= reg_data
						  >> (DMA_OFFSET_SIZE*2 + SP_DMA_LENGTH_SIZE
						  + SP_DMA_COUNT_SIZE);
						read <= HIGH;
						end
					end

				SP_DMA_WRITE_LENGTH : begin
					if (dma_full) begin
						// set error bit
						$display("Panic!  DMA register double buffer overflow");
						$finish;
						end
					else begin
						// write skip, length, and count register
						// and begin a DMA write
						next_dma_full = HIGH;
						length <= reg_data >> DMA_OFFSET_SIZE;
						count <= reg_data
						  >> (DMA_OFFSET_SIZE + SP_DMA_LENGTH_SIZE);
						skip <= reg_data
						  >> (DMA_OFFSET_SIZE*2 + SP_DMA_LENGTH_SIZE
						  + SP_DMA_COUNT_SIZE);
						read <= LOW;
						end
					end
				endcase
			end

		if (io_status_reg_write) begin : io_status_block
			reg next_set_interrupt_on_break, next_clear_interrupt_on_break;
			reg [SP_SIGNAL_SIZE-1:0] next_set_signal, next_clear_signal;
			reg next_set_single_step, next_clear_single_step;
			reg next_set_interrupt, next_clear_interrupt;
			reg next_clear_broke;
			reg next_set_halt, next_clear_halt;

			{
			  next_set_signal[7], next_clear_signal[7],
			  next_set_signal[6], next_clear_signal[6],
			  next_set_signal[5], next_clear_signal[5],
			  next_set_signal[4], next_clear_signal[4],
			  next_set_signal[3], next_clear_signal[3],
			  next_set_signal[2], next_clear_signal[2],
			  next_set_signal[1], next_clear_signal[1],
			  next_set_signal[0], next_clear_signal[0],
			  next_set_interrupt_on_break, next_clear_interrupt_on_break,
			  next_set_single_step, next_clear_single_step,
			  next_set_interrupt, next_clear_interrupt,
			  next_clear_broke,
			  next_set_halt, next_clear_halt
			} = cbus_data_reg;

			set_interrupt_on_break
			  = next_set_interrupt_on_break | set_interrupt_on_break;
			clear_interrupt_on_break
			  = next_clear_interrupt_on_break | clear_interrupt_on_break;
			set_signal = next_set_signal | set_signal;
			clear_signal = next_clear_signal | clear_signal;
			set_single_step = next_set_single_step | set_single_step;
			clear_single_step = next_clear_single_step | clear_single_step;
			set_interrupt = next_set_interrupt | set_interrupt;
			clear_interrupt = next_clear_interrupt | clear_interrupt;
			clear_broke = next_clear_broke | clear_broke;
			set_halt = next_set_halt | set_halt;
			clear_halt = next_clear_halt | clear_halt;
			end

		if (cp0_status_reg_write) begin : cp0_status_block
			reg next_set_interrupt_on_break, next_clear_interrupt_on_break;
			reg [SP_SIGNAL_SIZE-1:0] next_set_signal, next_clear_signal;
			reg next_set_single_step, next_clear_single_step;
			reg next_set_interrupt, next_clear_interrupt;
			reg next_clear_broke;
			reg next_set_halt, next_clear_halt;

			{
			  next_set_signal[7], next_clear_signal[7],
			  next_set_signal[6], next_clear_signal[6],
			  next_set_signal[5], next_clear_signal[5],
			  next_set_signal[4], next_clear_signal[4],
			  next_set_signal[3], next_clear_signal[3],
			  next_set_signal[2], next_clear_signal[2],
			  next_set_signal[1], next_clear_signal[1],
			  next_set_signal[0], next_clear_signal[0],
			  next_set_interrupt_on_break, next_clear_interrupt_on_break,
			  next_set_single_step, next_clear_single_step,
			  next_set_interrupt, next_clear_interrupt,
			  next_clear_broke,
			  next_set_halt, next_clear_halt
			} = cp0_data_in;

			set_interrupt_on_break
			  = next_set_interrupt_on_break | set_interrupt_on_break;
			clear_interrupt_on_break
			  = next_clear_interrupt_on_break | clear_interrupt_on_break;
			set_signal = next_set_signal | set_signal;
			clear_signal = next_clear_signal | clear_signal;
			set_single_step = next_set_single_step | set_single_step;
			clear_single_step = next_clear_single_step | clear_single_step;
			set_interrupt = next_set_interrupt | set_interrupt;
			clear_interrupt = next_clear_interrupt | clear_interrupt;
			clear_broke = next_clear_broke | clear_broke;
			set_halt = next_set_halt | set_halt;
			clear_halt = next_clear_halt | clear_halt;
			end


		// caluculate the length of the DMA, assuming a 2K byte page boundary
		// and a 16 cycle block boundary
		// Note: transfer_length = # bytes to transfer - 1
		//       max_page = # bytes left on RDRAM page - 1
		//       SP_DMA_MAX_BLOCK = max number of DMA clocks - 1
		max_page = ~slave_address_sum;
		if (length_sum > SP_DMA_MAX_BLOCK) begin
			if (SP_DMA_MAX_BLOCK > max_page) begin
				transfer_length <= max_page;
				end
			else begin
				transfer_length <= SP_DMA_MAX_BLOCK;
				end
			end
		else begin
			if (length_sum > max_page) begin
				transfer_length <= max_page;
				end
			else begin
				transfer_length <= length_sum;
				end
			end


		// DMA request state machine
		case (request_state)
			STATE_REQUEST_IDLE : begin
				if (io_read_full || io_write_full) begin
					io_valid <= HIGH;
					request_state <= STATE_REQUEST_IO;
					end
				else if (dma_full) begin
					slave_address_adder0 = slave_address;
					slave_address_adder1 = 0;
					slave_address_adder2 = LOW;
					master_address_adder0 = master_address;
					master_address_adder1 = -1;
					length_adder0 = length;
					length_adder1 = -1;
					load_count = HIGH;
					next_dma_full = LOW;
					next_dma_busy = HIGH;

					skip_pl <= skip;
					length_pl <= length;
					read_pl <= read;
					imem_select_pl <= master_imem_select;

					dma_request <= HIGH;
					request_state <= STATE_REQUEST_DMA;
					end
				else begin
					request_state <= STATE_REQUEST_IDLE;
					end
				end

			STATE_REQUEST_IO : begin
				// wait for IO to complete
				if (io_valid) begin
					request_state <= STATE_REQUEST_IO;
					end
				else begin
					request_state <= STATE_REQUEST_IDLE;
					end
				end

			STATE_REQUEST_DMA : begin
				// request the cbus if the slave device is ready
				// Note: we will be in this state for at lease two cycles, so
				//       transfer_length will be valid before it is needed
				next_dma_busy = HIGH;
		
				// wait for the cbus to be granted
				if (dma_grant) begin
					// calculate the start of the next DMA
					slave_address_adder0 = slave_address_sum;
					slave_address_adder1 = transfer_length;
					slave_address_adder2 = HIGH;
					master_address_adder0 = master_address_sum;
					master_address_adder1 = transfer_length;
					length_adder0 = length_sum;
					length_adder1 = transfer_length;
					next_mem_busy = HIGH;

					dma_imem_select_pl <= imem_select_pl;
					dma_mem_address_pl <= master_address_sum;
					dma_read_pl <= read_pl;
					dma_valid <= HIGH;

					dma_request <= LOW;
					request_state <= STATE_REQUEST_NEXT;
					end
				else begin
					dma_request <= HIGH;
					request_state <= STATE_REQUEST_DMA;
					end
				end

			STATE_REQUEST_NEXT : begin
				if (~&length_sum) begin
					// generate a new DMA request which continues the current span
					next_dma_busy = HIGH;
					request_state <= STATE_REQUEST_DMA;
					end
				else if (count_sum > 0) begin
					// generate a new DMA request for the next span
					next_dma_busy = HIGH;
	
					// advance the DMA address
					slave_address_adder0 = slave_address_sum;
					slave_address_adder1 = skip_pl;
					slave_address_adder2 = LOW;
					length_adder0 = length_pl;
					length_adder1 = -1;
					decrement_count = HIGH;
	
					request_state <= STATE_REQUEST_DMA;
					end
				else if (io_read_full || io_write_full) begin
					io_valid <= HIGH;
					request_state <= STATE_REQUEST_IO;
					end
				else if (dma_full) begin
					slave_address_adder0 = slave_address;
					slave_address_adder1 = 0;
					slave_address_adder2 = LOW;
					master_address_adder0 = master_address;
					master_address_adder1 = -1;
					length_adder0 = length;
					length_adder1 = -1;
					load_count = HIGH;
					next_dma_full = LOW;
					next_dma_busy = HIGH;

					skip_pl <= skip;
					length_pl <= length;
					read_pl <= read;
					imem_select_pl <= master_imem_select;

					dma_request <= HIGH;
					request_state <= STATE_REQUEST_DMA;
					end
				else begin
					request_state <= STATE_REQUEST_IDLE;
					end
				end

			default : begin
				request_state <= 'bx;

				$display("Panic! Unknown MSP request state - <%d>", request_state);
				$finish;
				end
			endcase


		// DMA transfer state machine
		case (dma_state)
			STATE_DMA_IDLE : begin
				if (dma_valid) begin
					next_mem_busy = HIGH;
					if (dma_start) begin
						load_dma_mem_address = HIGH;
						dma_valid <= LOW;
						if (dma_read_pl) begin
							next_mem_write = HIGH;
							next_mem_mask = -1;
							if (dma_last) begin
								if (dma_valid) begin
									next_dma_busy = HIGH;
									end
								dma_state <= STATE_DMA_IDLE;
								end
							else begin
								next_dma_busy = HIGH;
								dma_state <= STATE_READ_SECONDARY;
								end
							end
						else begin
							next_mem_read = HIGH;
							if (dma_last) begin
								if (dma_valid) begin
									next_dma_busy = HIGH;
									end
								dma_state <= STATE_DMA_IDLE;
								end
							else begin
								next_dma_busy = HIGH;
								dma_state <= STATE_WRITE_SECONDARY;
								end
							end
						end
					else begin
						next_dma_busy = HIGH;
						dma_state <= STATE_DMA_IDLE;
						end
					end
				else begin
					dma_state <= STATE_DMA_IDLE;
					end
				end

			STATE_WRITE_PRIMARY : begin
				next_mem_read = HIGH;
				next_mem_busy = HIGH;

				if (dma_last) begin
					if (dma_valid) begin
						next_dma_busy = HIGH;
						end
					dma_state <= STATE_DMA_IDLE;
					end
				else begin
					next_dma_busy = HIGH;
					dma_state <= STATE_WRITE_SECONDARY;
					end
				end

			STATE_WRITE_SECONDARY : begin
				if (imem_select) begin
					next_mem_read = HIGH;
					end

				if (dma_last) begin
					if (dma_valid) begin
						next_dma_busy = HIGH;
						next_mem_busy = HIGH;
						end
					dma_state <= STATE_DMA_IDLE;
					end
				else begin
					next_dma_busy = HIGH;
					next_mem_busy = HIGH;
					dma_state <= STATE_WRITE_PRIMARY;
					end
				end

			STATE_READ_PRIMARY : begin
				next_mem_write = HIGH;
				next_mem_mask = -1;
				next_mem_busy = HIGH;

				if (dma_last) begin
					if (dma_valid) begin
						next_dma_busy = HIGH;
						end
					dma_state <= STATE_DMA_IDLE;
					end
				else begin
					next_dma_busy = HIGH;
					dma_state <= STATE_READ_SECONDARY;
					end
				end

			STATE_READ_SECONDARY : begin
				next_mem_mask = -1;

				if (imem_select) begin
					next_mem_write = HIGH;
					end
				
				if (dma_last) begin
					if (dma_valid) begin
						next_dma_busy = HIGH;
						next_mem_busy = HIGH;
						end
					dma_state <= STATE_DMA_IDLE;
					end
				else begin
					next_dma_busy = HIGH;
					next_mem_busy = HIGH;
					dma_state <= STATE_READ_PRIMARY;
					end
				end

			default: begin
				dma_state <= 'bx;
				$display("Panic! Unknown MSP DMA state - <%d>", dma_state);
				$finish;
				end
			endcase


		// CMDBUF state machine
		case (cmd_state)
			STATE_CMD_PRIMARY : begin
				if (cmd_read && cmd_ready) begin
					// read from DMEM into CMDBUF
					next_mem_read = HIGH;
					cmd_state <= STATE_CMD_SECONDARY;
					end
				else begin
					cmd_state <= STATE_CMD_PRIMARY;
					end
				end

			STATE_CMD_SECONDARY : begin
				cmd_state <= STATE_CMD_PRIMARY;
				end

			default : begin
				cmd_state <= 'bx;
				end
			endcase


		// IO MEM read/write state machine
		// An IO read may occur during an IO write, but not vice-versa.
		// Therefore, if we always give IO write preference, we will
		// always execute in-order without preemption.  Also, a write
		// will not occur during a write nor will a read occur during
		// a read.

		case (io_state)
			STATE_IO_IDLE : begin
				if (io_valid && !mem_busy) begin
					load_io_mem_address = HIGH;
					if (io_write_full) begin
						if (next_io_imem_select) begin
							next_mem_read = HIGH;
							io_state <= STATE_IO_IMEM_WRITE_1;
							end
						else begin
							next_mem_write = HIGH;
							if (next_io_word_select) begin
								next_mem_mask = 2'b01;
								end
							else begin
								next_mem_mask = 2'b10;
								end
							io_state <= STATE_IO_WRITE;
							end
						end
					else begin
						next_mem_read = HIGH;
						io_state <= STATE_IO_READ_1;
						end
					end
				else begin
					io_state <= STATE_IO_IDLE;
					end
				end

			STATE_IO_READ_1 : begin
				io_valid <= LOW;
				io_read_full <= LOW;
				io_state <= STATE_IO_READ_2;
				end

			STATE_IO_READ_2 : begin
				io_state <= STATE_IO_READ_3;
				end

			STATE_IO_READ_3 : begin
				next_mem_load = HIGH;
				io_state <= STATE_IO_IDLE;
				end

			STATE_IO_IMEM_WRITE_1 : begin
				io_state <= STATE_IO_IMEM_WRITE_2;
				end

			STATE_IO_IMEM_WRITE_2 : begin
				io_state <= STATE_IO_IMEM_WRITE_3;
				end

			STATE_IO_IMEM_WRITE_3 : begin
				load_io_mem_address = HIGH;
				next_mem_write = HIGH;
				io_state <= STATE_IO_WRITE;
				end

			STATE_IO_WRITE : begin
				io_valid <= LOW;
				io_write_full <= LOW;
				io_state <= STATE_IO_IDLE;
				end

			default : begin
				io_state <= 'bx;
				end
			endcase

		pc_write <= next_pc_write;
		mem_read <= next_mem_read;
		mem_write <= next_mem_write;
		mem_load <= next_mem_load;
		dma_full <= next_dma_full;
		dma_busy <= next_dma_busy || next_dma_full;
		mem_busy <= next_mem_busy;
		bist_done_reg <= next_bist_done;
		bist_fail_reg <= next_bist_fail;
		cpu_semaphore_read <= next_cpu_semaphore_read;
		cpu_semaphore_write <= next_cpu_semaphore_write;

		semaphore <= cp0_semaphore_read || cpu_semaphore_read
		  || (!cp0_semaphore_write && !cpu_semaphore_write && semaphore);

		if (cpu_semaphore_read) begin
			cpu_semaphore <= (semaphore && !cp0_semaphore_write)
			  || cp0_semaphore_read;
			end

		case ({set_broke, clear_broke})
			2'b10 : begin
				broke <= HIGH;
				set_halt = HIGH;
				if (interrupt_on_break) begin
					set_interrupt = HIGH;
					end
				end
			2'b01 : broke <= LOW;
			endcase

		case ({set_halt, clear_halt})
			2'b10 : halt <= HIGH;
			2'b01 : halt <= LOW;
			endcase

		case ({set_interrupt, clear_interrupt})
			2'b10 : interrupt <= HIGH;
			2'b01 : interrupt <= LOW;
			endcase

		case ({set_single_step, clear_single_step})
			2'b10 : single_step <= HIGH;
			2'b01 : single_step <= LOW;
			endcase

		begin : signal_block
			integer i;
			for (i = 0; i < SP_SIGNAL_SIZE; i = i + 1) begin
				case ({set_signal[i], clear_signal[i]})
					2'b10 : signal[i] <= HIGH;
					2'b01 : signal[i] <= LOW;
					endcase
				end
			end

		case ({set_interrupt_on_break, clear_interrupt_on_break})
			2'b10 : interrupt_on_break <= HIGH;
			2'b01 : interrupt_on_break <= LOW;
			endcase

		reg_read_request <= next_reg_read_request;
		mem_read_request <= next_mem_read_request;

		master_address_sum <= master_address_adder0+master_address_adder1+1;

		slave_address_sum <= slave_address_adder0
		  + slave_address_adder1
		  + slave_address_adder2;
	

		length_sum <= length_adder0 + ~length_adder1;

		mem_address <= mem_address_sum;

		if (load_count) begin
			count_sum <= count;
			end
		else if (decrement_count) begin
			count_sum <= count_sum - 1;
			end
	
		// dma adders
		if (cmd_read && cmd_ready) begin
			imem_select <= LOW;
			mem_address_sum <= cmd_address;
			end
		else if (load_io_mem_address) begin
			io_write_select <= HIGH;
			io_read_select <= next_io_word_select;
			imem_select <= next_io_imem_select;
			mem_address_sum <= next_io_mem_address;
			end
		else if (load_dma_mem_address) begin
			io_write_select <= LOW;
			imem_select <= dma_imem_select_pl;
			mem_address_sum <= dma_mem_address_pl;
			end
		else begin
			mem_address_sum <= mem_address_sum + 1;
			end
	
		// dmem write mask
		mem_mask <= next_mem_mask;
		end
	end

endmodule