pi_logic.tmg
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/************************************************************************/
/* SYNOPSIS SCRIPT */
/************************************************************************/
/************************************************************************/
/* Synthesis parameters */
/************************************************************************/
module = pi_logic
clock = clock
wire_load = 256000
standard_load = 0.01
dflt_input_delay = 2.0
dflt_output_delay = 14.0
dflt_pin_delay = 10.0
dflt_input_load = 20
dflt_output_load = 20
dflt_pin_load = 150
dflt_drive_cell = dfntnh
dflt_drive_pin = q
dflt_max_transition = 2.0
default_uncertainty = 1.0
/************************************************************************/
/* Clock and reset constraints */
/************************************************************************/
create_clock clock -period 16.0 -waveform {0.0 8.0}
set_dont_touch_network clock
set_clock_skew -propagated -uncertainty default_uncertainty clock
set_max_fanout 0.02 reset_l
/************************************************************************/
/* Default synthesis constraints */
/************************************************************************/
set_input_delay dflt_input_delay -clock clock all_inputs()
set_input_delay 0 clock
set_load dflt_input_load * standard_load all_inputs()
set_output_delay dflt_output_delay -clock clock all_outputs()
set_load dflt_output_load * standard_load all_outputs()
set_driving_cell -cell dflt_drive_cell -pin dflt_drive_pin all_inputs()
set_max_transition dflt_max_transition current_design
set_drive 0 clock
set_driving_cell -none clock
set_arrival 0 clock
/************************************************************************/
/* Default operating conditions and environment */
/************************************************************************/
set_operating_conditions NOM
/************************************************************************/
/* Module specific timing constraints */
/************************************************************************/
set_driving_cell -cell ni01d5 { cbus_read_enable cbus_write_enable }
set_driving_cell -cell ni01d5 { dbus_enable }
set_input_delay 5.0 -clock clock { cbus_read_enable }
set_input_delay 5.0 -clock clock { cbus_write_enable }
set_input_delay 5.0 -clock clock { dbus_enable }
set_driving_cell -cell nt01d5 { cbus_data dbus_data }
set_load 200 * standard_load { cbus_data dbus_data }
set_input_delay 10.0 -clock clock { cbus_data dbus_data }
set_output_delay 6.0 -clock clock { cbus_data dbus_data }
set_driving_cell -cell ni01d5 { dma_start dma_last }
set_load 100 * standard_load { dma_start dma_last }
set_max_fanout 10 * standard_load { dma_start dma_last }
set_driving_cell -cell ni01d5 { cbus_command cbus_select }
set_load 200 * standard_load { cbus_command cbus_select }
set_max_fanout 10 * standard_load { cbus_command cbus_select }
set_load dflt_pin_load * standard_load \
{ ad16_data_out ad16_aleh ad16_alel }
set_output_delay dflt_pin_delay -clock clock \
{ ad16_data_out ad16_aleh ad16_alel }