rcp_partition.ss
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = "rcp"
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = search_path + "../../syn" + "../../inc"
read -format db ../../syn/rcp.db
/*****************************************************************************/
/* break up the hierarchy */
/*****************************************************************************/
current_design = rcp
link
/*****************************************************************************/
/* group rdp */
/*****************************************************************************/
current_design = rdp
ungroup {cs, at, ep, ms, st}
/* cs_ew_cv_block */
group { cs/clklogic, cs/gclklogic, ew, cv, at/atew } \
-design_name cs_ew_cv -cell_name cs_ew_cv
group { cs_ew_cv, cs/msbbuf, cs/lsbbuf } \
-design_name cs_ew_cv_grp -cell_name cs_ew_cv_grp
/* cc_logic */
group { cc, st/bluestepper, st/redstepper, st/greenstepper, st/alphastepper, \
ep/epcc, at/atcc } -design_name cc_logic -cell_name cc_logic
/* bl_logic */
group { bl, st/depthstepper, at/atbl } -design_name bl_logic -cell_name bl_logic
/* tc_logic */
group { tc, st/sstepper, st/tstepper, st/wstepper, st/lstepper, ep/eptc, \
at/attc } -design_name tc_logic -cell_name tc_logic
/* tm_block */
current_design = tm
group {low_half, hi_half, tm_logic} \
-design_name tm_grp -cell_name tm_grp
current_design = tm_grp
ungroup {low_half, hi_half}
current_design = rdp
ungroup {tm}
/* ms_upper */
current_design = rdp
group {ms/ms_upr, at/atms } -design_name ms_upper -cell_name ms_upper
/* ms_lower */
group {ms/ms_lwr, ms/sb0, ms/sb1} -design_name ms_lower -cell_name ms_lower
/* ms_grp */
group {ms_upper, ms_lower} -design_name ms_grp -cell_name ms_grp
/* tf_logic */
group { tm/mux2, tm/copy_load_bufs, tf } -design_name tf_logic -cell_name tf_logic
/*****************************************************************************/
/* group rsp */
/*****************************************************************************/
current_design = rsp
ungroup { vu }
/* io_logic */
group {io_cmd_dma, io_mem_dma, rspbusses} -design_name io_logic -cell_name io_logic
/*****************************************************************************/
/* group rcp */
/*****************************************************************************/
/* vi */
current_design = vi
group { vclk_blk clk_blk } -design_name vi_logic -cell_name vi_logic
group { spanbufa spanbufb vi_logic } -design_name vi_grp -cell_name vi_grp
current_design = rcp
/* if_logic */
group {ai_0, si_0, mi_0, arb_0} -design_name if_logic -cell_name if_logic
ungroup {rsp_0, rdp_0}
/* pads */
ungroup {pad_0}
group {pad_0/IOpad081, pad_0/IOpad082, pad_0/IOpad083, pad_0/IOpad084, pad_0/IOpad085, \
pad_0/IOpad086, pad_0/IOpad087, pad_0/IOpad088, pad_0/IOpad089, pad_0/IOpad090, \
pad_0/IOpad091, pad_0/IOpad092, pad_0/IOpad094, pad_0/IOpad095, \
pad_0/IOpad096, pad_0/IOpad097, pad_0/IOpad098, pad_0/IOpad099, pad_0/IOpad100, \
pad_0/IOpad101, pad_0/IOpad102, pad_0/IOpad103, pad_0/IOpad104, pad_0/IOpad105, \
pad_0/IOpad106, pad_0/IOpad107, pad_0/IOpad108, pad_0/IOpad109, \
pad_0/IOpad111, pad_0/IOpad112, pad_0/IOpad113, pad_0/IOpad114, pad_0/IOpad115, \
pad_0/IOpad116, pad_0/IOpad117, pad_0/IOpad118, pad_0/IOpad119, pad_0/IOpad120, \
pad_0/syn_clk_buftop1 \
} -design_name top_pads -cell_name top_pads
group {pad_0/IOpad001, pad_0/IOpad002, pad_0/IOpad003, pad_0/IOpad004, pad_0/IOpad005, \
pad_0/IOpad006, pad_0/IOpad007, pad_0/IOpad008, pad_0/IOpad009, pad_0/IOpad010, \
pad_0/IOpad011, pad_0/IOpad012, pad_0/IOpad013, pad_0/IOpad014, \
pad_0/IOpad016, pad_0/IOpad017, pad_0/IOpad018, pad_0/IOpad019, pad_0/IOpad020, \
pad_0/IOpad021, pad_0/IOpad022, pad_0/IOpad023, pad_0/IOpad024, pad_0/IOpad025, \
pad_0/IOpad026, pad_0/IOpad027, pad_0/IOpad028, pad_0/IOpad029, pad_0/IOpad030, \
pad_0/IOpad031, pad_0/IOpad033, pad_0/IOpad034, pad_0/IOpad035, \
pad_0/IOpad036, pad_0/IOpad037, pad_0/IOpad038, pad_0/IOpad039, pad_0/IOpad040, \
pad_0/syn_clk_bufbot1 \
} -design_name bot_pads -cell_name bot_pads
group {pad_0/IOpad121, pad_0/IOpad122, pad_0/IOpad123, pad_0/IOpad124, pad_0/IOpad125, \
pad_0/IOpad126, pad_0/IOpad160, \
rac_0, pad_0/syn_clk_buftop0, pad_0/syn_clk_bufbot0, g_0 \
} -design_name left_pads -cell_name left_pads
group {pad_0/IOpad041, pad_0/IOpad042, pad_0/IOpad043, pad_0/IOpad044, pad_0/IOpad045, \
pad_0/IOpad046, pad_0/IOpad047, pad_0/IOpad048, pad_0/IOpad049, pad_0/IOpad050, \
pad_0/IOpad051, pad_0/IOpad052, pad_0/IOpad053, pad_0/IOpad054, pad_0/IOpad055, \
pad_0/IOpad056, pad_0/IOpad057, pad_0/IOpad058, pad_0/IOpad059, pad_0/IOpad060, \
pad_0/IOpad061, pad_0/IOpad062, pad_0/IOpad063, pad_0/IOpad064, pad_0/IOpad065, \
pad_0/IOpad066, pad_0/IOpad067, pad_0/IOpad068, pad_0/IOpad069, pad_0/IOpad070, \
pad_0/IOpad071, pad_0/IOpad072, pad_0/IOpad073, pad_0/IOpad074, pad_0/IOpad075, \
pad_0/IOpad076, pad_0/IOpad077, pad_0/IOpad078, pad_0/IOpad079, pad_0/IOpad080 \
} -design_name right_pads -cell_name right_pads
/*****************************************************************************/
/* netlist modifications */
/*****************************************************************************/
current_design = rcp
all_connected reset_l_0
disconnect_net reset_l_0 -all
connect_net reset_l_0 tst_0/tst_reset_l_0
connect_net reset_l_0 rsp_0/su/reset_l
create_net reset_l_1
connect_net reset_l_1 tst_0/tst_reset_l_1
connect_net reset_l_1 rdp_0/bl_logic/reset_l
connect_net reset_l_1 rdp_0/cc_logic/reset_l
create_net reset_l_2
connect_net reset_l_2 tst_0/tst_reset_l_2
connect_net reset_l_2 rsp_0/vu/vusl01/reset_l
connect_net reset_l_2 rsp_0/vu/vusl23/reset_l
connect_net reset_l_2 rsp_0/vu/vusl45/reset_l
connect_net reset_l_2 rsp_0/vu/vusl67/reset_l
create_net reset_l_3
connect_net reset_l_3 tst_0/tst_reset_l_3
connect_net reset_l_3 if_logic/reset_l_0
connect_net reset_l_3 rsp_0/io_logic/reset_l
connect_net reset_l_3 pi_0/reset_l
create_net reset_l_4
connect_net reset_l_4 tst_0/tst_reset_l_4
connect_net reset_l_4 rdp_0/cs_ew_cv_grp/reset_l
connect_net reset_l_4 rdp_0/tc_logic/reset_l
create_net reset_l_5
connect_net reset_l_5 tst_0/tst_reset_l_5
connect_net reset_l_5 rsp_0/vu/div1/Reset_l
connect_net reset_l_5 rsp_0/vu/vurfctl1/reset_l
connect_net reset_l_5 rsp_0/vu/vdpregfile_i/reset_l
create_net reset_l_6
connect_net reset_l_6 tst_0/tst_reset_l_6
connect_net reset_l_6 rsp_0/ls/reset_l
connect_net reset_l_6 ri_0/reset_l
create_net reset_l_7
connect_net reset_l_7 tst_0/tst_reset_l_7
connect_net reset_l_7 rdp_0/ms_grp/reset_l
create_net reset_l_8
connect_net reset_l_8 tst_0/tst_reset_l_8
connect_net reset_l_8 rdp_0/tm/tm_grp/reset_l
create_net reset_l_9
connect_net reset_l_9 tst_0/tst_reset_l_9
connect_net reset_l_9 vi_0/reset_l
connect_net reset_l_9 vclk_driver_0/reset_l
/* create top-level spare nets */
current_design = left_pads
create_port spare_port0 -direction "out"
create_port spare_port1 -direction "out"
create_net spare_net0
create_net spare_net1
create_cell spare_net_driver0 ne35hd130d/in01d5
create_cell spare_net_driver1 ne35hd130d/in01d5
create_net VSS
connect_net VSS spare_net_driver0/i
connect_net spare_net0 spare_net_driver0/zn
connect_net spare_net0 spare_port0
connect_net VSS spare_net_driver1/i
connect_net spare_net1 spare_net_driver1/zn
connect_net spare_net1 spare_port1
current_design = right_pads
create_port spare_port0 -direction "in"
create_port spare_port1 -direction "in"
current_design = rcp
link
create_net spare_net0
connect_net spare_net0 left_pads/spare_port0
connect_net spare_net0 right_pads/spare_port0
create_net spare_net1
connect_net spare_net1 left_pads/spare_port1
connect_net spare_net1 right_pads/spare_port1
/*****************************************************************************/
/* reports */
/*****************************************************************************/
current_design = rcp
check_design > rcp_partition.lint
report_hierarchy
/*****************************************************************************/
/* cadence defaults */
/*****************************************************************************/
include "cadence_defaults.dc"
/*****************************************************************************/
/* write design */
/*****************************************************************************/
/* write the entire design into one db file */
write -format db -hierarchy -o rcp_partition.db rcp
/* write the top-level and group nets into one edif file */
write -format edif -o rcp_top.edf rcp
quit