/*****************************************************************************/
/* custom variables                                                          */
/*****************************************************************************/
module = suctl
wire_load = 256000
standard_load = 0.01
clock = clk
default_input_delay = 1.5
default_output_delay = 1.0
default_input_load = 20
default_output_load = 20
default_drive_cell = dfntnh
default_drive_pin = q

/*****************************************************************************/
/* set the path and read                                                     */
/*****************************************************************************/
search_path = {. \
	/ecad/synopsys/current/libraries/syn \
	/ecad/reality/lib/synopsys/nec35_v2.1 \
	/ecad/reality/lib/synopsys/rcp_lib \
	../src };

read -f verilog ../src/suctl.v
read -f edif suvuctl.edf
read -f edif suotherctl.edf
read -f edif issue.edf
read -f edif vt_decode.edf

current_design = module

/*****************************************************************************/
/* default environment                                                       */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top

/*****************************************************************************/
/* default constraint                                                        */
/*****************************************************************************/
/* set_max_area 0 */
set_dont_touch { ne35hd130d/nt01d* }
create_clock clock -period 16.0 -waveform {0.0 8.0}

set_input_delay default_input_delay -clock clock all_inputs()
set_output_delay default_output_delay -clock clock all_outputs()
set_load default_output_load * standard_load all_outputs()
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs()

/*****************************************************************************/
/* clock and reset constraints                                               */
/*****************************************************************************/
set_drive 0 clock
set_arrival 0 clock
set_dont_touch_network clock

set_driving_cell -cell ni01d5 -pin z reset_l

/*****************************************************************************/
/* custom constraints                                                        */
/*****************************************************************************/
set_max_transition 2.0 module
include module + ".con"

/*****************************************************************************/
/* check                                                                     */
/*****************************************************************************/
check_design > module + ".lint"
link

set_fix_hold all_clocks()
set_clock_skew -uncertainty 1 clock

write -format edif -hierarchy -o "pre" + module + ".edf" module
report_constraint -all_violators > "prereport." + module + ".viol"
report_timing -to all_outputs() -nets -max_paths 50 > "prereport." + module + ".output"
report_timing -from all_inputs() -max_paths 50 >  "prereport." + module + ".input"

/*****************************************************************************/
/* compile                                                                   */
/*****************************************************************************/

current_design issue
set_dont_touch su_inst_unit
set_dont_touch vu_inst_unit
set_dont_touch pc_mux*
set_dont_touch kill_unit
set_dont_touch hazard_unit
set_dont_touch *muxed_inst*

set_dont_touch *mx_clr_taken*
set_dont_touch *mx_set_taken*
set_dont_touch *mx_wr_taken*
set_dont_touch *mx_xpose_*_*
set_dont_touch *st_xpose_buf*
set_dont_touch *halt_pc_mux*

current_design suotherctl
set_dont_touch *_mx*
set_dont_touch rd_base_buf*
set_dont_touch rd_offset_buf*
set_dont_touch *surdamux_unit*

current_design module
set_dont_touch vt_decode
set_dont_touch suvuctl

current_design module
compile -map_effort high -incremental_mapping -boundary_optimization

current_design issue
set_dont_touch su_inst_unit false
set_dont_touch vu_inst_unit false
set_dont_touch pc_mux* false
set_dont_touch kill_unit false
set_dont_touch hazard_unit false
set_dont_touch *muxed_inst* false
set_dont_touch *mx_clr_taken* false
set_dont_touch *mx_set_taken* false
set_dont_touch *mx_wr_taken* false
set_dont_touch *mx_xpose_*_* false
set_dont_touch *st_xpose_buf* false
set_dont_touch *halt_pc_mux* false

current_design suotherctl
set_dont_touch *_mx* false
set_dont_touch rd_base_buf* false
set_dont_touch rd_offset_buf* false
set_dont_touch *surdamux_unit* false

current_design module
set_dont_touch vt_decode false
set_dont_touch suvuctl false

compile -prioritize_min_paths -incremental_mapping -only_design_rule

report_area
report -reference
report_constraint -all_violators > "report." + module + ".viol"
report_timing -to all_outputs() -nets -max_paths 50 > "report." + module + ".output"
report_timing -from all_inputs() -max_paths 50 >  "report." + module + ".input"

write -format edif -hierarchy -o module + ".edf" module
write -format verilog -hierarchy -o module + ".vsyn" module
write -format db -hierarchy -o module + ".db" module

quit