set_input_delay  2.5 -clock clk { surf_wen };
set_input_delay  11.0 -clock clk { surf_w };
set_input_delay  7.0 -clock clk { surf_ra };
set_input_delay  7.0 -clock clk { surf_rb };
set_input_delay  8.0 -clock clk {suwben};

set_input_delay  10.8 -clock clk {suimmlsmux};
set_input_delay  10.2 -clock clk {suimmmux};
set_input_delay  10.2 -clock clk {suvulsoffsetmux};
set_input_delay  11.2 -clock clk {surdbmux};
set_input_delay  1.0 -clock clk {sudrivels};
set_input_delay  11.2 -clock clk {surdamux};

set_input_delay  6.0 -clock clk {sushbmux};
set_input_delay  6.0 -clock clk {sushamux};
set_input_delay  8.0 -clock clk {suslten};
set_input_delay  8.0 -clock clk {sualuen};
set_input_delay  2.0 -clock clk {sualu_cin};
set_input_delay  2.0 -clock clk {sualu};
set_input_delay  2.0 -clock clk {sualuamux};
set_input_delay  2.0 -clock clk {sualubmux};
set_input_delay  7.0 -clock clk {inst_data};
set_input_delay  2.0 -clock clk {link_pc_delay_pc};
set_input_delay  12.5 -clock clk {susltlt};
set_input_delay  4.85  -clock clk {shiftamt};

set_input_delay  12.0 -clock clk {ls_data};

set_output_delay -max 11.0  -clock clk {suonesdet_z};
set_output_delay -max 6.0  -clock clk {sualu_ovr};
set_output_delay -max 5.5  -clock clk {sualu_cout};
set_output_delay -max 14.0   -clock clk {suexbsign};
set_output_delay -max 2.0  -clock clk {sushvamt};
set_output_delay -max 14.0   -clock clk {suexasign};
set_output_delay -max  5.0 -clock clk {sualumsb};

set_output_delay -max 8.0  -clock clk {branch_or_addr};
set_output_delay  -max 12.0 -clock clk {ls_data};

set_driving_cell -cell ni01d7 -pin z { "inst_data[6]" }
set_driving_cell -cell ni01d7 -pin z { "inst_data[15]" }
set_driving_cell -cell nt01d5 -pin z { ls_data }


set_load 2.0 {ls_data};
/* set_load 1.0 {sushvamt} 	buffer rd_base in suctl */