/*****************************************************************************/
/* custom variables                                                          */
/*****************************************************************************/
module = "pad"
wire_load = 256000
clocks = { "clock" "gclk" }
standard_load = 0.01
default_input_delay = 1.5
default_output_delay = 14.0
default_input_load = 20
default_output_load = 20
default_drive_cell = "dfntnh"
default_drive_pin = "q"
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 1.0

/*****************************************************************************/
/* set the path and read                                                     */
/*****************************************************************************/
search_path = search_path + ".." + "../inc"

read -format verilog src/pad.v

link

check_design

/*****************************************************************************/
/* write design                                                              */
/*****************************************************************************/
write -format edif -hierarchy -o module + ".edf" module

quit