vi_dma.ss
4.28 KB
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/*****************************************************************************/
/* custom variables */
/*****************************************************************************/
module = vi_dma
wire_load = 256000
standard_load = 0.01
clock = clk
default_input_delay = 1.5
default_output_delay = 14.0
default_input_load = 20
default_output_load = 20
default_drive_cell = dfntnh
default_drive_pin = q
default_period = 16.0
default_max_transition = 1.5
default_uncertainty = 0.5
hdlin_force_use_ffgen = false
/*****************************************************************************/
/* set the path and read */
/*****************************************************************************/
search_path = search_path \
+ "../src" \
+ "../../inc" \
+ "../../../lib/verilog/user" \
+ "../../syn"
read -f verilog cbus_driver.v
read -f verilog module + ".v"
/*****************************************************************************/
/* default environment */
/*****************************************************************************/
set_operating_conditions NOM
set_wire_load wire_load -mode top
/*****************************************************************************/
/* clock and reset constraints */
/*****************************************************************************/
create_clock clock -period default_period -waveform { 0.0 default_period / 2 }
set_clock_skew -propagated -uncertainty default_uncertainty clock
set_dont_touch_network clock
/*****************************************************************************/
/* default constraint */
/*****************************************************************************/
set_max_area 0
set_dont_touch { ne35hd130d/nt01d* }
set_input_delay default_input_delay -clock clock all_inputs() > /dev/null
set_output_delay default_output_delay -clock clock all_outputs() > /dev/null
set_load default_output_load * standard_load all_outputs() > /dev/null
set_load default_input_load * standard_load all_inputs() > /dev/null
set_driving_cell -cell default_drive_cell -pin default_drive_pin all_inputs() > /dev/null
set_drive 0 { clock reset_l }
set_input_delay 8 -clock clk reset_l
set_max_transition default_max_transition current_design
/*****************************************************************************/
/* custom constraints */
/*****************************************************************************/
set_driving_cell -cell ni01d5 { cbus_read_enable cbus_write_enable }
set_driving_cell -cell nt01d4 { cbus_data }
set_load 200 * standard_load { cbus_data }
set_input_delay 2.0 -clock clock { cbus_data }
set_output_delay 4.0 -clock clock { cbus_data }
set_driving_cell -cell ni01d5 { cbus_command cbus_select }
set_load 100 * standard_load { cbus_command cbus_select }
set_max_fanout 10 * standard_load { cbus_command cbus_select }
set_input_delay 12.0 -clock clock { dma_address }
set_input_delay 12.0 -clock clock { dma_length }
set_input_delay 12.0 -clock clock { reg_read_data }
set_output_delay 13.0 -clock clock { read_request }
set_load 2.0 { read_request }
set_min_porosity 75
/*****************************************************************************/
/* check */
/*****************************************************************************/
check_design > module + ".lint"
/*****************************************************************************/
/* compile */
/*****************************************************************************/
compile -map_effort high -ungroup_all -routability
/*****************************************************************************/
/* write */
/*****************************************************************************/
include "report.dc"
write -format edif -hierarchy -o module + ".edf" module
write -format db -hierarchy -o module + ".db" module
quit