si_v.tst
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//****************************************************************************
//
// File: si.tst
// Test file for Serial Interface (SI)
//
// $Revision: 1.1.1.1 $
//
// File Format:
//
// t <id> <arg1> <arg2> <arg3> <arg4> - Run test id with the 4 args
// where id = decimal number
// argX = hex number
// q - Quit testing and shutdown verilog
// server
//
//
//****************************************************************************
//****************************************************************************
// Configure RDRAM
t 0000 00000000 00000000 00000000 00000000
// Init RDRAM with pattern data (rdram_addr, nbytes, pattern_key)
t 0013 00000000 00000080 81234567 00000000
//****************************************************************************
// W/R data into SI DRAM address reg -> SHOULD PASS
// HW resets the data to be word-aligned with upper 2 bytes zeroed out
// Test SI DRAM Address Reg: address, data
t 0103 04800000 012468C2 002468C0 00000000
//****************************************************************************
// Read pre-loaded data from PIF and compare -> SHOULD PASS
// (assuming pre-loaded data contains data = (address >> 2) & 0x0000FFFF)
// Test SI IO RD: address, data to compare
t 0101 1fc00004 00000001 00000000 00000000
t 0101 1fc00008 00000002 00000000 00000000
t 0101 1fc007bc 000001ef 00000000 00000000
t 0101 1fc007c4 000001f1 00000000 00000000
//****************************************************************************
// Test SI DMA: type (1=RD4B, 2=WR4B, 3=RD64B, 4=WR64B),
// pif_address, dram_address
//****************************************************************************
// IO Read 4 Bytes PIF -> DRAM (on word-aligned) -> SHOULD PASS
t 0031 1fc007c0 000001f0 00000000 00000000
t 0031 1fc00004 00000001 00000000 00000000
//****************************************************************************
// Io Write/Read 4 Bytes PIF <- DRAM -> SHOULD PASS
t 0032 1fc007cc 12345678 00000000 00000000
// Interrupt should be set due to IO write - test for interrupt bit
t 0104 04800018 00001000 00000000 00000000
// Reset interrupt by writing into status reg
t 0102 04800018 00000000 00000000 00000000
// Now, test for interrupt bit to be reset
t 0104 04800018 00001000 00000001 00000000
//****************************************************************************
// DMA 64 Bytes from PIF to DRAM (on 8B-aligned) -> SHOULD PASS
t 0033 00000003 1fc007c0 00000008 00000000
// Now, test for DMA busy bit
t 0104 04800018 00000001 00000001 00000000
// Now, test for interrupt bit
t 0104 04800018 00001000 00000000 00000000
// Reset interrupt bit
t 0102 04800018 00000000 00000000 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 1fc007c0 00000008 00000040 00000000
//****************************************************************************
// DMA 64 Bytes from DRAM to PIF (on 8B-aligned) -> SHOULD PASS
t 0033 00000004 1fc007c0 00000040 00000000
// Now, test for DMA busy bit
t 0104 04800018 00000001 00000001 00000000
// Now we compare data (pif_address, dram_address, nbytes)
t 0105 1fc007c0 00000040 00000040 00000000
//****************************************************************************
// QUIT
//****************************************************************************
q