Skip to content

Barry / rf-depot

Go to a project
Toggle navigation
Toggle navigation pinning
Switch branch/tag
issue2.s 22.5 KB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 
/****************************************************************
  This program improves toggle coverage for the instruction
  issue logic.
	
  Alignment of instructions to 64-bit boundaries, and misalignment
  with respect to 64-bit boundaries, is critical for testing
  issue logic.  Removal of nop's will cause changes in this
  alignment.
 ****************************************************************/

#include "suregre.h"

.base 0x04001000
        .data   0x04000000
        .word   0x00000000              /* Addr: 0x0000 */
        .word   0x00000000              /* Addr: 0x0004 */
        .word   0x00000000              /* Addr: 0x0008 */
        .word   0x00000000              /* Addr: 0x000C */
        .word   0x00000000              /* Addr: 0x0010 */
        .word   0x00000000              /* Addr: 0x0014 */
        .word   0x00000000              /* Addr: 0x0018 */
        .word   0x00000000              /* Addr: 0x001C */
        .word   0x00000000              /* Addr: 0x0020 */
        .word   0x00000000              /* Addr: 0x0024 */
        .word   0x00000000              /* Addr: 0x0028 */
        .word   0x00000000              /* Addr: 0x002C */
        .word   0x00000000              /* Addr: 0x0030 */
        .word   0x00000000              /* Addr: 0x0034 */
        .word   0x00000000              /* Addr: 0x0038 */
        .word   0x00000000              /* Addr: 0x003C */
        .word   0x00000000              /* Addr: 0x0040 */
        .word   0x00000000              /* Addr: 0x0044 */
        .word   0x00000000              /* Addr: 0x0048 */
        .word   0x00000000              /* Addr: 0x004C */
        .word   0x00000000              /* Addr: 0x0050 */
        .word   0x00000000              /* Addr: 0x0054 */
        .word   0x00000000              /* Addr: 0x0058 */
        .word   0x00000000              /* Addr: 0x005C */
        .word   0x00000000              /* Addr: 0x0060 */
        .word   0x00000000              /* Addr: 0x0064 */
        .word   0x00000000              /* Addr: 0x0068 */
        .word   0x00000000              /* Addr: 0x006C */
        .word   0x00000000              /* Addr: 0x0070 */
        .word   0x00000000              /* Addr: 0x0074 */
        .word   0x00000000              /* Addr: 0x0078 */
        .word   0x00000000              /* Addr: 0x007C */
        .word   0x9F9C6781              /* Addr: 0x0080 */
        .word   0x52C6B5FB              /* Addr: 0x0084 */
        .word   0x3EDE2F54              /* Addr: 0x0088 */
        .word   0xAF7F61DF              /* Addr: 0x008C */
        .word   0xC737CDE1              /* Addr: 0x0090 */
        .word   0x804872BF              /* Addr: 0x0094 */
        .word   0xF7A31956              /* Addr: 0x0098 */
        .word   0x03F72847              /* Addr: 0x009C */
        .word   0x59867287              /* Addr: 0x00A0 */
        .word   0x6AB59488              /* Addr: 0x00A4 */
        .word   0xD673CEEA              /* Addr: 0x00A8 */
        .word   0x44E56A7B              /* Addr: 0x00AC */
        .word   0x615D29A1              /* Addr: 0x00B0 */
        .word   0x4F1D8B54              /* Addr: 0x00B4 */
        .word   0x0BD55B37              /* Addr: 0x00B8 */
        .word   0x996AE45B              /* Addr: 0x00BC */
        .word   0x00010001              /* Addr: 0x00C0 */
        .word   0x00010001              /* Addr: 0x00C4 */
        .word   0x00010001              /* Addr: 0x00C8 */
        .word   0x00010001              /* Addr: 0x00CC */
        .word   0xffffffff              /* Addr: 0x00D0 */
        .word   0xffffffff              /* Addr: 0x00D4 */
        .word   0xffffffff              /* Addr: 0x00D8 */
        .word   0xffffffff              /* Addr: 0x00DC */
        .word   0x00030003              /* Addr: 0x00E0 */
        .word   0x00030003              /* Addr: 0x00E4 */
        .word   0x00030003              /* Addr: 0x00E8 */
        .word   0x00030003              /* Addr: 0x00EC */
        .word   0xBEE2018F              /* Addr: 0x00F0 */
        .word   0xD60B1305              /* Addr: 0x00F4 */
        .word   0x71690809              /* Addr: 0x00F8 */
        .word   0xD4DDCBCD              /* Addr: 0x00FC */

	.word   0x598629A1              /* Addr: 0x0100 */ 
	.word   0x0001ffff              /* Addr: 0x0104 */ 
	.word   0x00030009              /* Addr: 0x0108 */  
	.word   0x000A2847              /* Addr: 0x010C */ 
	.word   0x9F9CCDE1              /* Addr: 0x0110 */  
	.word   0x6AB58B54              /* Addr: 0x0114 */   
	.word   0x0001ffff              /* Addr: 0x0118 */   
	.word   0x000361DF              /* Addr: 0x011C */  
	.word   0x598629A1              /* Addr: 0x0120 */   
	.word   0x0001ffff              /* Addr: 0x0124 */   
	.word   0x00030009              /* Addr: 0x0128 */ 
	.word   0x000A2847              /* Addr: 0x012C */  


	/* Clear performance counters */
	ori	r1, r0, 0x3c0
	mtc0	r1, r11
	
	/* The following line is the difference between issue1.s and
	issue2.s */
	nop
	
        LI(r0 , 0xFFFF, 0xFFFF);
        LI(r1 , 0x0101, 0x0101);
        LI(r2 , 0x0202, 0x0202);
        LI(r3 , 0x0303, 0x0303);
        LI(r4 , 0x0404, 0x0404);
        LI(r5 , 0x0505, 0x0505);
        LI(r6 , 0x0606, 0x0606);
        LI(r7 , 0x0707, 0x0707);
        LI(r8 , 0x0808, 0x0808);
        LI(r9 , 0x0909, 0x0909);
        LI(r10, 0x0A0A, 0x0A0A);
        LI(r11, 0x0B0B, 0x0B0B);
        LI(r12, 0x0C0C, 0x0C0C);
        LI(r13, 0x0D0D, 0x0D0D);
        LI(r14, 0x0E0E, 0x0E0E);
        LI(r15, 0x0F0F, 0x0F0F);
        LI(r16, 0x1010, 0x1010);
        LI(r17, 0x1111, 0x1111);
        LI(r18, 0x1212, 0x1212);
        LI(r19, 0x1313, 0x1313);
        LI(r20, 0x1414, 0x1414);
        LI(r21, 0x1515, 0x1515);
        LI(r22, 0x1616, 0x1616);
        LI(r23, 0x1717, 0x1717);
        LI(r24, 0x1818, 0x1818);
        LI(r25, 0x1919, 0x1919);
        LI(r26, 0x1A1A, 0x1A1A);
        LI(r27, 0x1B1B, 0x1B1B);
        LI(r28, 0x1C1C, 0x1C1C);
        LI(r29, 0x1D1D, 0x1D1D);
        LI(r30, 0x1E1E, 0x1E1E);
        LI(r31, 0x1F1F, 0x1F1F);

        lqv     v0[0], 0 (r0);
        vxor    v0 , v0, v0
        vxor    v1 , v0, v0
        vxor    v2 , v0, v0
        vxor    v3 , v0, v0
        vxor    v4 , v0, v0
        vxor    v5 , v0, v0
        vxor    v6 , v0, v0
        vxor    v7 , v0, v0
        vxor    v8 , v0, v0
        vxor    v9 , v0, v0
        vxor    v10, v0, v0
        vxor    v11, v0, v0
        vxor    v12, v0, v0
        vxor    v13, v0, v0
        vxor    v14, v0, v0
        vxor    v15, v0, v0
        vxor    v16, v0, v0
        vxor    v17, v0, v0
        vxor    v18, v0, v0
        vxor    v19, v0, v0
        vxor    v20, v0, v0
        vxor    v21, v0, v0
        vxor    v22, v0, v0
        vxor    v23, v0, v0
        vxor    v24, v0, v0
        vxor    v25, v0, v0
        vxor    v26, v0, v0
        vxor    v27, v0, v0
        vxor    v28, v0, v0
        vxor    v29, v0, v0
        vxor    v30, v0, v0
        vxor    v31, v0, v0

	ori	r31, r0, 0xff
	ori	r29, r0, 0x800
	ori	r24, r0, 0xa00
	
/* *** issue_kill_unit_f_s_haz_first_vu_us2 *** */
/* *** issue_kill_unit_f_s_haz_first_vu_us2a *** */
/* *** issue_kill_unit_f_s_haz_term_vu9 *** */
/* *** issue_kill_unit_f_s_haz_term_vu_c *** */
/* *** issue_kill_unit_s_f_haz_second_ctcf_vc2 *** */
/* check that vu use_vc2/ctc2_vc2 are not dual issued */

	addi	r1, r0, 0x0
	ctc2	r0, v0
	lqv	v5, 0xd0(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	ori 	r4, r0, 0x93
	ctc2	r4, v2
	ctc2	r0, v1
	ori 	r4, r0, 0xff
	ctc2	r4, v0
	ori	r27, r0, 0x93
	nop
	vnoop
	vcl	v7, v5, v6
	ctc2	r0, v2
	nop
	nop
	nop
	nop
	cfc2	r30, v1
	bne	r30, r27, Fail
	sqv	v7, 0(r29)
	mfc0	r23, r12
	sw	r23, 0(r24)
	
	addi	r1, r0, 0x1
	ctc2	r0, v0
	lqv	v5, 0xd0(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	ori 	r4, r0, 0x93
	ctc2	r4, v2
	ctc2	r0, v1
	ori 	r4, r0, 0xff
	ctc2	r4, v0
	ori	r27, r0, 0x93
	nop
	vnoop
	vch	v7, v5, v6
	ctc2	r0, v2
	nop
	nop
	nop
	nop
	cfc2	r30, v1			/* fix */
	bne	r30, r4, Fail
	sqv	v7, 0x10(r29)
	mfc0	r23, r12
	sw	r23, 4(r24)
	

	addi	r1, r0, 0x2
	ctc2	r0, v0
	lqv	v5, 0xd0(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	ori 	r4, r0, 0x93
	ctc2	r4, v2
	ctc2	r0, v1
	ori 	r4, r0, 0xff
	ctc2	r4, v0
	ori	r27, r0, 0x93
	nop
	vnoop
	vcr	v7, v5, v6
	ctc2	r0, v2
	nop
	nop
	nop
	nop
	cfc2	r30, v1			/* fix */
	bne	r30, r4, Fail
	sqv	v7, 0x20(r29)
	mfc0	r23, r12
	sw	r23, 8(r24)
	

/* *** issue_kill_unit_s_f_haz_term_su0 *** */
/* check that vu load/use_vs are not dual issued */
	
	addi	r1, r0, 0x3
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop
	lqv	v5, 0x80(r0)
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x30(r29)
	mfc0	r23, r12
	sw	r23, 0xc(r24)
	
	
/* *** issue_kill_unit_s_f_haz_term_su1 *** */
/* check that vu load/use_vt are not dual issued */
	
	addi	r1, r0, 0x4
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop
	lqv	v6, 0x80(r0)
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x40(r29)
	mfc0	r23, r12
	sw	r23, 0x10(r24)

/* *** issue_kill_unit_s_f_haz_term_su2 *** */
/* check that vu load/write_vd are not dual issued */
	
	addi	r1, r0, 0x5
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x80(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop
	lqv	v7, 0x90(r0)
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x50(r29)
	mfc0	r23, r12
	sw	r23, 0x14(r24)

/* *** issue_kill_unit_f_s_haz_term_su3 *** */
/* check that vu mtc2/use_vs are not dual issued */

	addi	r1, r0, 0x6
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop				/* aligned */	/* s_f */
	mtc2	r1, v5[2]
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[2]
	bne	r28, r1, Fail
	sqv	v7, 0x60(r29)
	mfc0	r23, r12
	sw	r23, 0x18(r24)

/* *** issue_kill_unit_f_s_haz_term_su4 *** */
/* *** issue_kill_unit_f_s_haz_term_su_b *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* check that vu mtc2/use_vt are not dual issued */
	
	addi	r1, r0, 0x7
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop
	mtc2	r1, v6[2]
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[2]
	bne	r28, r1, Fail
	sqv	v7, 0x70(r29)
	mfc0	r23, r12
	sw	r23, 0x1c(r24)

/* *** issue_kill_unit_f_s_haz_term_su5 *** */
/* *** issue_kill_unit_f_s_haz_term_su_b *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* check that vu mtc2/write_vd are not dual issued */
	
	addi	r1, r0, 0x8
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop
	mtc2	r1, v7[2]
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x80(r29)
	mfc0	r23, r12
	sw	r23, 0x20(r24)

/* *** issue_kill_unit_f_s_haz_term_su6 *** */
/* *** issue_kill_unit_f_s_haz_term_su_b *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* *** issue_xpose_1_c *** */
/* check that vu ltv/use_vs+ are not dual issued */
	
	addi	r1, r0, 0x9
	ctc2	r0, v0
	sh	r1, 0x8a(r0)
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop
	ltv	v0[0], 0x80(r0)
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[10]
	bne	r28, r1, Fail
	sqv	v7, 0x90(r29)
	mfc0	r23, r12
	sw	r23, 0x24(r24)

/* *** issue_kill_unit_f_s_haz_term_su7 *** */
/* *** issue_kill_unit_f_s_haz_term_su_b *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* check that vu ltv/use_vt+ are not dual issued */
	
	addi	r1, r0, 0xa
	ctc2	r0, v0
	sh	r1, 0x8c(r0)
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)	
	nop
	ltv	v0[0], 0x80(r0)
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[12]
	bne	r28, r1, Fail
	sqv	v7, 0xa0(r29)
	mfc0	r23, r12
	sw	r23, 0x28(r24)

/* *** issue_kill_unit_f_s_haz_term_su8 *** */
/* *** issue_kill_unit_f_s_haz_term_su_c *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* check that vu ltv/write_vd+ are not dual issued */
	
	addi	r1, r0, 0xb
	ctc2	r0, v0
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	nop
	nop
	ltv	v0[0], 0x80(r0)
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	mfc2	r28, v7[14]
	bne	r28, r0, Fail
	sqv	v7, 0xb0(r29)
	mfc0	r23, r12
	sw	r23, 0x2c(r24)

/* *** issue_kill_unit_f_s_haz_term_su9 *** */
/* *** issue_kill_unit_f_s_haz_term_su_c *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* check that vu ctc2_vc0/use_vc0 are not dual issued */
	
	addi	r1, r0, 0xc
	ctc2	r0, v0
	addi	r2, r0, 0xff
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0xc0(r0)	
	nop
	ctc2	r2, v0
	vadd	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0xc0(r29)
	mfc0	r23, r12
	sw	r23, 0x30(r24)

	addi	r1, r0, 0xd
	ctc2	r0, v0
	addi	r2, r0, 0xff
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0xc0(r0)	
	nop
	ctc2	r2, v0
	veq	v7, v5, v6
	nop
	nop
	nop
	nop
	veq	v9, v7, v5
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0xd0(r29)
	mfc0	r23, r12
	sw	r23, 0x34(r24)

/* *** issue_kill_unit_f_s_haz_term_su10 *** */
/* *** issue_kill_unit_f_s_haz_term_su_c *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* check that vu ctc2_vc1/use_vc1 are not dual issued */

	ori	r5, r0, 0x80
	addi	r1, r0, 0xe
	ctc2	r0, v0
	addi	r2, r0, 0xff
	lqv	v5, 0x70(r0)	
	lqv	v6, 0x80(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	lsv	v8[2], 0x2(r5)	
	lsv	v8[4], 0x4(r5)	
	lsv	v8[8], 0x8(r5)
	ori	r5, r0, 0x16
	nop
	nop
	ctc2	r5, v1
	vmrg	v7, v6, v5
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0xe0(r29)
	mfc0	r23, r12
	sw	r23, 0x38(r24)

/* *** issue_kill_unit_f_s_haz_term_su11 *** */
/* *** issue_kill_unit_f_s_haz_term_su_c *** */
/* *** issue_kill_unit_sav_su_first_hazard *** */
/* *** issue_kill_unit_f_s_haz_first_ctc2_vc2 *** */
/* *** issue_kill_unit_f_s_haz_second_vu_us2 *** */
/* *** issue_kill_unit_f_s_haz_second_vu_us2a *** */
/* check that vu ctc2_vc2/use_vc2 are not dual issued */

	addi	r1, r0, 0xf
	ctc2	r0, v0
	lqv	v5, 0xd0(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	ctc2	r0, v1
	ori 	r4, r0, 0xff
	ctc2	r4, v0
	ori	r28, r0, 0x0093
	ori 	r4, r0, 0x93
	nop
	nop
	ctc2	r4, v2
	vcl	v7, v5, v6
	nop
	nop
	nop
	nop
	cfc2	r30, v1
	bne	r30, r28, Fail
	sqv	v7, 0xf0(r29)
	mfc0	r23, r12
	sw	r23, 0x3c(r24)

	addi	r1, r0, 0x10
	ctc2	r0, v0
	lqv	v5, 0xd0(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	ctc2	r0, v1
	ori 	r4, r0, 0xff
	ctc2	r4, v0
	ori	r28, r0, 0x0093
	ori 	r4, r0, 0x93
	nop
	nop
	ctc2	r4, v2
	vch	v7, v5, v6
	nop
	nop
	nop
	nop
	cfc2	r30, v1
	bne	r30, r31, Fail		/* Fix this */
	sqv	v7, 0x100(r29)
	mfc0	r23, r12
	sw	r23, 0x40(r24)

	addi	r1, r0, 0x11
	ctc2	r0, v0
	lqv	v5, 0xd0(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x70(r0)	
	ctc2	r0, v1
	ori 	r4, r0, 0xff
	ctc2	r4, v0
	ori	r28, r0, 0x0093
	ori 	r4, r0, 0x93
	nop
	nop
	ctc2	r4, v2
	vxor	v7, v5, v6
	nop
	nop
	nop
	nop
	cfc2	r30, v1
	bne	r30, r0, Fail		/* Fix this */
	sqv	v7, 0x110(r29)
	mfc0	r23, r12
	sw	r23, 0x44(r24)

/* *** issue_kill_unit_f_s_haz_term_vu2 *** */
/* check that vu dest/mfc2 dest are not dual issued */
	
	addi	r1, r0, 0x12
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lh	r28, 0x80(r0)
	nop
	vnoop
	vxor	v7, v5, v6
	mfc2	r30, v7[0]
	nop
	nop
	nop
	nop
	bne	r30, r28, Fail
	sqv	v7, 0x120(r29)
	mfc0	r23, r12
	sw	r23, 0x48(r24)

/* *** issue_kill_unit_f_s_haz_term_vu3 *** */
/* check that vu dest/mtc2 dest are not dual issued */
	
	addi	r1, r0, 0x13
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lqv	v8, 0x80(r0)
	mtc2	r1, v8[0]
	nop
	vnoop
	vxor	v7, v5, v6
	mtc2	r1, v7[0]
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x130(r29)
	mfc0	r23, r12
	sw	r23, 0x4c(r24)

/* *** issue_kill_unit_f_s_haz_term_vu5 *** */
/* check that vu write/store are not dual issued */
	
	addi	r1, r0, 0x14
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lhu	r8, 0x8e(r0)	
	vnoop
	vxor	v7, v5, v6
	stv	v0[0], 0xf0(r0)
	nop
	nop
	nop
	nop
	lhu	r30, 0xfe(r0)	
	bne	r30, r8, Fail
	sqv	v7, 0x140(r29)
	mfc0	r23, r12
	sw	r23, 0x50(r24)

/* *** issue_kill_unit_f_s_haz_term_vu6 *** */
/* check that vu write/vu lwv are not dual issued */
	
	addi	r1, r0, 0x15
	ctc2	r0, v0
	lqv	v5, 0x80(r0)	
	lqv	v6, 0x70(r0)	
	lqv	v7, 0x70(r0)	
	lhu	r8, 0x8e(r0)
	nop
	vnoop
	vxor	v7, v5, v6
	lwv	v0[0], 80(r0)
	nop
	nop
	nop
	nop
	mfc2	r30, v7[14]
	bne	r30, r8, Fail
	sqv	v7, 0x150(r29)
	mfc0	r23, r12
	sw	r23, 0x54(r24)

/* *** issue_kill_unit_f_s_haz_term_vu7 *** */
/* check that vu use_vc0/ctc2_vc0 are not dual issued */
	
	addi	r1, r0, 0x16
	ori	r4, r0, 0xff
	ctc2	r4, v0
	lqv	v5, 0xc0(r0)	
	lqv	v6, 0xc0(r0)
	lqv	v7, 0x70(r0)	
	lqv	v8, 0xe0(r0)	
	vnoop
	vadd	v7, v5, v6
	ctc2	r0, v0
	ctc2	r0, v1
	nop
	nop
	nop
	nop
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x160(r29)
	mfc0	r23, r12
	sw	r23, 0x58(r24)

	addi	r1, r0, 0x17
	ori	r4, r0, 0xff
	ctc2	r4, v0
	lqv	v5, 0xc0(r0)	
	lqv	v6, 0xc0(r0)
	lqv	v7, 0x70(r0)	
	lqv	v8, 0xe0(r0)	
	vnoop
	vge	v7, v5, v6
	ctc2	r0, v0
	ctc2	r0, v1
	nop
	nop
	nop
	nop
	veq	v9, v7, v6
	cfc2	r30, v1
	bne	r30, r31, Fail
	sqv	v7, 0x170(r29)
	mfc0	r23, r12
	sw	r23, 0x5c(r24)

/* *** issue_kill_unit_f_s_haz_term_vu8 *** */
/* *** issue_kill_unit_f_s_haz_term_vu_c *** */
/* check that vu write_vc1/cfc2_vc1 are not dual issued */
/* this is done in the previous test */
/*	
	vnoop				aligned	s_f 
	veq	vd, vs, vt
	cfc2	rx, v1

	vnoop			 	f_s 
	veq	vd, vs, vt	 	aligned 
	cfc2	rx, v1
*/
	
/* *** issue_muxed_sav_xp *** */
/* *** issue_sav_xpose *** */
/* *** issue_st_xpose_fst *** */
/* *** issue_st_xpose_snd *** */
/* *** issue_rd_xpose_fst *** */
/* *** issue_rd_xpose_snd *** */
/* *** issue_xpose_1_a *** */
/* *** issue_xpose_1_b *** */
/* *** issue_xpose_1_d *** */
/* *** issue_xpose_2_a *** */
/* *** issue_xpose_2_b *** */
/* check the issue of transpose instructions */

	addi	r1, r0, 0x18
	lqv	v16, 0x80(r0)
	lqv	v17, 0x90(r0)
	lqv	v18, 0xa0(r0)
	lqv	v19, 0xb0(r0)
	lqv	v20, 0xc0(r0)
	lqv	v21, 0xd0(r0)
	lqv	v22, 0xe0(r0)
	lqv	v23, 0xf0(r0)

	lqv	v24, 0xa0(r0)
	lqv	v25, 0xb0(r0)
	lqv	v26, 0xc0(r0)
	lqv	v27, 0xd0(r0)
	lqv	v28, 0xe0(r0)
	lqv	v29, 0xf0(r0)
	lqv	v30, 0x80(r0)
	lqv	v31, 0x90(r0)
	
	nop
	nop
	and	r17, r15, r16
	vxor	v14, v15, v16
	and	r27, r25, r26
	vxor	v7, v5, v6
	vnoop
	stv	v24[0], 0x180(r29)	/* rd_xpose_snd */
	nop				/* muxed_sav_xp <- st_xpose_snd */
	stv	v16[0], 0x190(r29)	/* rd_xpose_snd */
	nop				/* muxed_sav_xp <- rd_xpose_snd */
	lqv	v7, 0x180(r29)
	lqv	v8, 0x100(r0)
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	nop

	addi	r1, r0, 0x19
	lqv	v7, 0x190(r29)
	lqv	v8, 0x110(r0)
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	nop

	addi	r1, r0, 0x1a
	nop	
	and	r17, r15, r16
	vxor	v14, v15, v16
	and	r27, r25, r26
	vxor	v7, v5, v6
	stv	v24[0], 0x1a0(r29)	/* rd_xpose_fst */
	nop
	lqv	v7, 0x1a0(r29)
	lqv	v8, 0x120(r0)
	veq	v9, v7, v8
	cfc2	r30, v1
	bne	r30, r31, Fail
	nop
	mfc0	r23, r12
	sw	r23, 0x60(r24)

/*	
   assign rd_xpose_snd = rd_inst[31] && (rd_inst[14:11]==4'b1011);
   assign rd_xpose_fst = rd_inst[63] && (rd_inst[46:43]==4'b1011);
   spasdffen_1_0 fst_xp_vu_ff (st_xpose_snd, st_xpose_snd_n, rd_xpose_snd, save_rd_inst, clk, reset_l);
   spasdffen_1_0 snd_xp_vu_ff (st_xpose_fst, st_xpose_fst_n, rd_xpose_fst, save_rd_inst, clk, reset_l);
   assign muxed_sav_xp =prev_stalled ? st_xpose_snd : rd_xpose_snd;
   spasdffen_1_0 su_sav_xp_ff (sav_xpose, sav_xpose_n, muxed_sav_xp,adv_ir, clk,reset_l);
   assign save_rd_inst = should_have_stalled && !prev_stalled;
   spasdff_1_0_h prev_imem_stall_ff (prev_stalled, prev_stalled_n, should_have_stalled, clk, reset_l);	
   nr02d3 nr_su_sel_enc_0 (.a1(fst_rd_vu_custom), .a2(odd_target_custom), .zn(su_inst_sel_enc[0]));

   nd02d2 nd_su_sel_enc_1a (.a1(loc_prev_stalled), .a2(fst_st_vu), .zn(su_sel_enc_1a));
   nd02d2 nd_su_sel_enc_1b (.a1(loc_prev_stalled), .a2(odd_target_custom), .zn(su_sel_enc_1b));
   nd03d2 nd_su_sel_enc_1 (.a1(su_sel_enc_1a), .a2(su_sel_enc_1b), .a3(sav_su_n), .zn(su_inst_sel_enc[1]));
   nd03d2 nd_su_sel_enc_3 (.a1(su_sel_enc_1a), .a2(su_sel_enc_1b), .a3(sav_su_n), .zn(su_inst_sel_enc[3]));
   nd03d2 nd_su_sel_enc_4 (.a1(su_sel_enc_1a), .a2(su_sel_enc_1b), .a3(sav_su_n), .zn(su_inst_sel_enc[4]));
   nd03d2 nd_su_sel_enc_5 (.a1(su_sel_enc_1a), .a2(su_sel_enc_1b), .a3(sav_su_n), .zn(su_inst_sel_enc[5]));
   mx21d1h mx_xpose_1_a (.i0(rd_xpose_snd), .i1(st_xpose_snd), .s(su_inst_sel_enc[1]), .z(xpose_1_a));
   mx21d1h mx_xpose_1_b (.i0(rd_xpose_fst), .i1(st_xpose_snd), .s(su_inst_sel_enc[3]), .z(xpose_1_b));
   mx21d1h mx_xpose_1_d (.i0(st_xpose_fst), .i1(sav_xpose), .s(su_inst_sel_enc[5]), .z(xpose_1_d));
   mx21d1h mx_xpose_2_a (.i0(xpose_1_a), .i1(xpose_1_c), .s(su_inst_sel_enc[2]), .z(xpose_2_a));
   mx21d1h mx_xpose_2_b (.i0(xpose_1_b), .i1(xpose_1_d), .s(su_inst_sel_enc[2]), .z(xpose_2_b));
*/

/* *** issue_old_br_addr[11,9:7,5,3] *** */

	jal 0xfec	
	nop


        ori     r1, r0, 0xFEED;
Fail:
        sw      r1, 0(r0)
        nop
        nop
        nop
        nop
        break
	nop
	nop
	nop
	nop
	nop

	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	
	jr	r31
	nop

	break			/* should never get here */
	nop
	nop