bl_test.v 3.91 KB
// Verilog model created from schematic bl_test.sch
// 2002/06/04 7:13:41 PM
// vericode v2.1


     // Schematic 'bl_test.sch'
module bl_test;
  wire [7:0]  BLEND_MASK;
  wire [1:0]  Z_MOD;
  wire [1:0]  CVG_DEST;
  wire [1:0]  P0;
  wire [1:0]  M0;
  wire [1:0]  A0;
  wire [1:0]  B0;
  wire [1:0]  P1;
  wire [1:0]  M1;
  wire [1:0]  A1;
  wire [1:0]  B1;
  wire [7:0]  BR;
  wire [7:0]  BG;
  wire [7:0]  BB;
  wire [7:0]  FR;
  wire [7:0]  FG;
  wire [7:0]  FB;
  wire [7:0]  FA;
  wire [7:0]  PIX_R;
  wire [7:0]  PIX_G;
  wire [7:0]  PIX_B;
  wire [7:0]  PIX_A;
  wire [3:0]  PIX_CVG;
  wire [7:0]  SHADE_A;
  wire [17:0]  ST_Z;
  wire [15:0]  DZDX;
  wire [15:0]  DZDY;
  wire [15:0]  PRIM_Z;
  wire [15:0]  PRIM_DZ;
  wire [7:0]  MEM_R;
  wire [7:0]  MEM_G;
  wire [7:0]  MEM_B;
  wire [2:0]  MEM_A;
  wire [17:0]  MEM_Z;
  wire [7:0]  SPAN_R;
  wire [7:0]  SPAN_G;
  wire [7:0]  SPAN_B;
  wire [7:0]  SPAN_A;
  wire [17:0]  SPAN_Z;
  wire  SPAN_Z_WE;
  wire  SPAN_CLR_WE;
  wire  MASK15B;
  wire  FRC_BLND;
  wire  CLR_ON_CVG;
  wire  Z_UPDATE_EN;
  wire  Z_COMP_EN;
  wire  AA_EN;
  wire  Z_SEL;
  wire  NCYC;
  wire  ST_SPAN;
  wire  CLK;

bl BL (.ANTIALIAS_ENABLE(AA_EN), .BL_A_SEL_0_R(BR[7:6]), .BL_A_SEL_1_R(A0[1:0]),
           .BL_B_SEL_0_R(A1[1:0]), .BL_B_SEL_1_R(B0[1:0]), .BL_M_SEL_0_R(B1[1:0]),
           .BL_M_SEL_1_R(M0[1:0]), .BL_P_SEL_0_R(M1[1:0]), .BL_P_SEL_1_R(P0[1:0]),
           .BLEND_B(BB[7:0]), .BLEND_G(BG[7:0]), .BLEND_R(BLEND_MASK[7:0]),
           .COLOR_ON_CVG(P1[1]), .CVG_DEST({ CLR_ON_CVG,  }), .DZDX({ CVG_DEST[1:0], 
           CVG_DEST[1:0], CVG_DEST[1:0], CVG_DEST[1:0], CVG_DEST[1:0], 
           CVG_DEST[1:0], CVG_DEST[1:0], CVG_DEST[1:0] }), .DZDY(DZDX[15:0]),
           .FOG_A(DZDY[15:8]), .FOG_B(FA[7:0]), .FOG_G(FB[7:0]), .FOG_R(FG[7:0]),
           .FORCE_BLEND(FR[7]), .GCLK(FRC_BLND), .MASK15B(CLK), .MEM_A({ MASK15B, 
            }), .MEM_B({ MEM_A[2:0], MEM_A[2:0], MEM_A[2:1] }), .MEM_G(MEM_B[7:0]),
           .MEM_R(MEM_G[7:0]), .MEM_Z({ MEM_R[7:0], MEM_R[7:0], MEM_R[7:6] }),
           .NCYC(MEM_Z[17]), .PIXEL_A({ NCYC,  }), .PIXEL_B(PIX_A[7:0]),
           .PIXEL_CVG(PIX_B[7:4]), .PIXEL_G({ PIX_CVG[3:0], PIX_CVG[3:0] }),
           .PIXEL_R(PIX_G[7:0]), .PRIM_DELTA_Z({ PIX_R[7:0], PIX_R[7:0] }),
           .PRIM_Z(PRIM_DZ[15:0]), .SHADE_A(PRIM_Z[15:8]), .SPAN_A({ Z_UPDATE_EN, 
            }), .SPAN_B(SPAN_A[7:0]), .SPAN_COLOR_WE(SPAN_B[7]), .SPAN_DEPTH_WE(SPAN_CLR_WE),
           .SPAN_G({ SPAN_Z_WE,  }), .SPAN_R(SPAN_G[7:0]), .SPAN_Z({ SPAN_R[7:0], 
           SPAN_R[7:0], SPAN_R[7:6] }), .ST_SPAN(SHADE_A[7]), .ST_Z({ ST_SPAN, 
            }), .Z_COMPARE_ENABLE(ST_Z[17]), .Z_MODE({ Z_COMP_EN,  }), .Z_SOURCE_SELECT(Z_MOD[1]),
           .Z_UPDATE_ENABLE(Z_SEL));
driver DRIVER (.ANTIALIAS_ENABLE(AA_EN), .BL_A_SEL_0_R(A0[1:0]),
           .BL_A_SEL_1_R(A1[1:0]), .BL_B_SEL_0_R(B0[1:0]), .BL_B_SEL_1_R(B1[1:0]),
           .BL_M_SEL_0_R(M0[1:0]), .BL_M_SEL_1_R(M1[1:0]), .BL_P_SEL_0_R(P0[1:0]),
           .BL_P_SEL_1_R(P1[1:0]), .BLEND_B(BB[7:0]), .BLEND_G(BG[7:0]),
           .BLEND_MASK(BLEND_MASK[7:0]), .BLEND_R(BR[7:0]), .COLOR_ON_CVG(CLR_ON_CVG),
           .CVG_DEST(CVG_DEST[1:0]), .DZDX(DZDX[15:0]), .DZDY(DZDY[15:0]),
           .FOG_A(FA[7:0]), .FOG_B(FB[7:0]), .FOG_G(FG[7:0]), .FOG_R(FR[7:0]),
           .FORCE_BLEND(FRC_BLND), .GCLK(CLK), .MASK15B(MASK15B),
           .MEM_A(MEM_A[2:0]), .MEM_B(MEM_B[7:0]), .MEM_G(MEM_G[7:0]),
           .MEM_R(MEM_R[7:0]), .MEM_Z(MEM_Z[17:0]), .NCYC(NCYC), .PIXEL_A({ PIX_A[7:0], 
           PIX_A[7] }), .PIXEL_B(PIX_B[7:0]), .PIXEL_CVG(PIX_CVG[3:0]),
           .PIXEL_G(PIX_G[7:0]), .PIXEL_R(PIX_R[7:0]), .PRIM_DELTA_Z(PRIM_DZ[15:0]),
           .PRIM_Z(PRIM_Z[15:0]), .SHADE_A(SHADE_A[7:0]), .ST_SPAN(ST_SPAN),
           .ST_Z(ST_Z[17:0]), .Z_COMPARE_ENABLE(Z_COMP_EN), .Z_MODE(Z_MOD[1:0]),
           .Z_SOURCE_SELECT(Z_SEL), .Z_UPDATE_ENABLE(Z_UPDATE_EN));

endmodule