////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module:      local.v
// description: parses command line arguments for verilog options.
//		included by rdp_v_16.v, which is created by 'xnet'.
//
//
//   Arguments:
//     -dump=<module>, flag to turn on dumpvars, dumps module (all levels)
//     -tmem=<texture mem file>, force loads a texture into 
//       texture memory.
//
// designer:    Rob Moore
// date:        10/18/94
//
////////////////////////////////////////////////////////////////////////


  reg [1:256*8] tmem;		// filename for Tmem contents
  reg [1:256*8] dumpname;	// name for dumpvars dump
  reg [63:0]	mem_word;	// word for loading Tmem
  reg [8:0]	i;		// index into Tmem
  integer	tfp;		// file pointer for Tmem file
  reg [31:0]	clk_count;	// count posedges 
  reg [31:0]	gclk_count;	// count posedges 
  integer	reg_chann;	// file handle for regression dump
  integer	reg_period;	// number of clocks between dumps
  integer	reg_clocks;	// number of clocks to dump


  reg		start_prim_d1;	// delay start_prim until y_cur valid
  reg		prim_dump_en;	// enable dumping based on primitive number
  reg		y_dump_en;	// enable dumping based on primitive number
  reg		in_y;		// enable dumping based on primitive number
  wire [11:0]	cur_y;		// current y
  reg [11:0]	min_y;		// smallest y to start dump on
  reg [11:0]	max_y;		// largest y to start dump on
  reg [31:0]	prim_number;	// prim number to dump
  reg [31:0]	prim_count;	// current prim number

  reg [1:256*8] qsim;		// filename for Qsim dump
  integer	qsim_chan;	// file handle for Qsim tab file
  integer	qsim_en;
  integer	first_edge;
  reg [1:256*8] ew_qsim;	// filename for EW Qsim dump
  integer	ew_qsim_chan;	// file handle for EW Qsim tab file
  integer	ew_qsim_en;
  integer	ew_first_edge;

  reg		first_prim_dv;	// used to validate ew-ms signals
  reg		first_prim_d1;	// used to validate ew-ms signals
  reg		first_prim_d2;	// used to validate ew-ms signals
  reg		first_prim_d3;	// used to validate ew-ms signals
  reg		first_prim_d4;	// used to validate ew-ms signals
  reg		first_prim_d5;	// used to validate ew-ms signals
  reg		first_prim_d6;	// used to validate ew-ms signals
  reg		first_prim_d7;	// used to validate ew-ms signals
  reg		first_prim_d8;	// used to validate ew-ms signals
  reg		first_prim_d9;	// used to validate ew-ms signals
  reg		first_prim_d10;	// used to validate ew-ms signals
  reg		first_prim_d11;	// used to validate ew-ms signals

  initial 
  begin
    clk_count = 0;
    if ($getnum$plusarg("reg_period=", reg_period) != 1)
      reg_period  = 100;
    if ($getnum$plusarg("reg_clocks=", reg_clocks) != 1)
      reg_clocks  = 10;
    if ($test$plusargs("reg_dump"))
      reg_chann = $fopen("regression_v.dump");
  end

  // Load Tmem
  initial
  begin
    if ($getstr$plusarg("tmem=", tmem) == 1)
    begin
      tfp = $open_mem_file(tmem);
      if (tfp == 0)
        $write("Cannot open Tmem file\n");
      else
      begin
	$write("Reading Tmem data %s\n", tmem);
        for(i = 0; i < 256; i = i + 1) // low Tmem addresses
        begin
          if(($read_mem_file(tfp, mem_word)) != -1)
          begin
            rdp_ms.tm.low_half.bnk0.ram_primh[i] = mem_word[63:56];
            rdp_ms.tm.low_half.bnk0.ram_priml[i] = mem_word[55:48];
            rdp_ms.tm.low_half.bnk1.ram_primh[i] = mem_word[47:40];
            rdp_ms.tm.low_half.bnk1.ram_priml[i] = mem_word[39:32];
            rdp_ms.tm.low_half.bnk2.ram_primh[i] = mem_word[31:24];
            rdp_ms.tm.low_half.bnk2.ram_priml[i] = mem_word[23:16];
            rdp_ms.tm.low_half.bnk3.ram_primh[i] = mem_word[15:8];
            rdp_ms.tm.low_half.bnk3.ram_priml[i] = mem_word[7:0];
          end
        end
        for(i = 0; i < 256; i = i + 1) // high Tmem addresses
        begin
          if(($read_mem_file(tfp, mem_word)) != -1)
          begin
            rdp_ms.tm.hi_half.bnk0.ram_primh[i] = mem_word[63:56];
            rdp_ms.tm.hi_half.bnk0.ram_priml[i] = mem_word[55:48];
            rdp_ms.tm.hi_half.bnk1.ram_primh[i] = mem_word[47:40];
            rdp_ms.tm.hi_half.bnk1.ram_priml[i] = mem_word[39:32];
            rdp_ms.tm.hi_half.bnk2.ram_primh[i] = mem_word[31:24];
            rdp_ms.tm.hi_half.bnk2.ram_priml[i] = mem_word[23:16];
            rdp_ms.tm.hi_half.bnk3.ram_primh[i] = mem_word[15:8];
            rdp_ms.tm.hi_half.bnk3.ram_priml[i] = mem_word[7:0];
          end
        end
      end
    end
  end

 
  // 
  //  dump file - set module to dump
  //
  initial
  begin
    if ($getstr$plusarg("dump=", dumpname) == 1)
    begin
      if(dumpname == "main")
        $dumpvars(4, main);
      else if(dumpname == "rdp_ms")
        $dumpvars(0, main.rdp_ms);
      else if(dumpname == "cs")
        $dumpvars(0, main.rdp_ms.cs);
      else if(dumpname == "ew")
        $dumpvars(0, main.rdp_ms.ew);
      else if(dumpname == "cv")
        $dumpvars(0, main.rdp_ms.cv);
      else if(dumpname == "ep")
        $dumpvars(0, main.rdp_ms.ep);
      else if(dumpname == "at")
        $dumpvars(0, main.rdp_ms.at);
      else if(dumpname == "tc")
        $dumpvars(0, main.rdp_ms.tc);
      else if(dumpname == "tm")
        $dumpvars(0, main.rdp_ms.tm);
      else if(dumpname == "tf")
        $dumpvars(0, main.rdp_ms.tf);
      else if(dumpname == "cc")
        $dumpvars(0, main.rdp_ms.cc);
      else if(dumpname == "bl")
        $dumpvars(0, main.rdp_ms.bl);
      else
        $dumpvars;

      if (($getnum$plusarg("prim=", prim_number) != 1) &&
	  (($getnum$plusarg("min_y=", min_y) != 1) ||
	   ($getnum$plusarg("max_y=", max_y) != 1)))
      begin
        $write("Turning on dumpvars\n");
	$dumpon;
      end
      else
      begin
        $write("Turning off dumpvars\n");
	$dumpoff;
      end
    end
  end

  //
  //  Dump when on primitive number specified  and between min line 
  //  and max line
  //
  initial
  begin
    //  clear variables
    prim_number = 0;
    prim_count  = 0;
    min_y       = 0;
    max_y       = 0;
    in_y        = 0;
    
    // get arguments
    if ($getnum$plusarg("prim=", prim_number) != 1)
	prim_dump_en = 0;
    else
    begin
	prim_dump_en = 1;
        prim_number = prim_number + 1;
    end

    if(($getnum$plusarg("min_y=", min_y) != 1) || 
	($getnum$plusarg("max_y=", max_y) != 1))
	y_dump_en = 0;
    else
	y_dump_en = 1;

    $write("prim_dump_en  = %h\n", prim_dump_en);
    $write("y_dump_en     = %h\n", y_dump_en);
    $write("prim          = %h\n", prim_number);
    $write("min_y         = %h\n", min_y);
    $write("max_y         = %h\n", max_y);

  end

`define NOT_SYNTHESIZED 1
`ifdef  NOT_SYNTHESIZED

  // debug stuff
  initial
  begin
    rdp_ms.ew.control.ew_ep_startspan_m = 0;
  end

  assign cur_y = main.rdp_ms.ew.rasterizer.scissory.y_cur[13:2];

  // Check prim and y loop
  always @(posedge gclock)
  begin

    // delay start_prim until y_cur loaded
    start_prim_d1 <= main.rdp_ms.cs.start_prim;

    // prim count == 1 on first prim
    if(start_prim_d1)
      prim_count <= prim_count + 1;

    if(prim_dump_en && y_dump_en)
    begin
      if(!in_y && (prim_count == prim_number) && (cur_y == min_y))
      begin
        $write("%d: p & y, Turning on dumpvars\n", $time);
        $dumpon;
	in_y = 1;
      end
      if(in_y && ((prim_count != prim_number) || (cur_y == max_y)))
      begin
        $write("%d: p & y, Turning off dumpvars\n", $time);
        $dumpoff;
        in_y = 0;
      end
    end

    else if(prim_dump_en && start_prim_d1)
    begin
      if(prim_count == prim_number)
      begin
        $write("%d: p, Turning on dumpvars\n", $time);
        $dumpon;
      end
      else
      begin
        $write("%d: p, Turning off dumpvars\n", $time);
        $dumpoff;
      end
    end

    else if(y_dump_en)
    begin
      if(!in_y && (cur_y == min_y))
      begin
        $write("%d: y,  Turning on dumpvars\n", $time);
        $dumpon;
        in_y = 1;
      end
      if(in_y && (cur_y == max_y))
      begin
        $write("%d: y, Turning off dumpvars\n", $time);
	$dumpoff;
        in_y = 0;
      end
    end

  end


  //
  //  Regression dumps
  //
  always @(posedge clock)
  begin
    
    if(($test$plusargs("reg_dump")) &&
	(clk_count >= 0) && 
      	((clk_count % reg_period) >= 0) &&
      	((clk_count % reg_period) < reg_clocks))
    begin
      $fwriteh(reg_chann, 
	clk_count,,
	rdp_ms.cs.cs_ew_data,,
	rdp_ms.cs.cs_ew_newprim,,
	rdp_ms.cs.ew_cs_busy,,
	rdp_ms.cs.attr_valid,,
	rdp_ms.cs.start_prim,,
	rdp_ms.ew.ew_ep_startspan,,
	rdp_ms.ew.ew_ep_d,,
	rdp_ms.ew.ew_stall_x,,
	rdp_ms.ew.ew_stall_attr,,
	rdp_ms.ew.left_xminor,,
	rdp_ms.ew.load_cmd_scissor,,
	rdp_ms.cv.ew_cv_newspan,,
	rdp_ms.cv.cv_value,,
	rdp_ms.cv.mask15,,
	rdp_ms.ep.st_span_bl,,
	rdp_ms.ep.st_span_cc,,
	rdp_ms.ep.st_span_ms,,
	rdp_ms.ep.st_span_tc,,
	rdp_ms.ep.st_span_tf,,
	rdp_ms.ep.st_span_st_r,,
	rdp_ms.ep.st_span_st_s,,
	rdp_ms.ep.st_span_st_w,,
	rdp_ms.ep.st_span_st_z,,
	rdp_ms.ep.tc_load,,
	rdp_ms.ep.tlut_en,,
	rdp_ms.at.tex_image,,
	rdp_ms.at.color_image,,
	rdp_ms.at.rel_sync_load,,
	rdp_ms.at.rel_sync_pipe,,
	rdp_ms.at.rel_sync_tile,,
	rdp_ms.at.strobe_sync_full,,
        "\n");
    end
    clk_count <= clk_count + 1;
  end

`endif   // NOT_SYNTHESIZED

  //
  //  Gclock counter
  //
  always @(posedge gclock)
    gclk_count <= gclk_count + 1;
    

  //
  //  Qsim Tabular File for RDP 
  //
  initial
  begin
    first_prim_dv  = 0;
    first_prim_d1  = 0;
    first_prim_d2  = 0;
    first_prim_d3  = 0;
    first_prim_d4  = 0;
    first_prim_d5  = 0;
    first_prim_d6  = 0;
    first_prim_d7  = 0;
    first_prim_d8  = 0;
    first_prim_d9  = 0;
    first_prim_d10 = 0;
    first_prim_d11 = 0;
  end

  always @(posedge clock)
  begin
      // used for validating ew-ms interface signals
      if(main.rdp_ms.cs.start_prim || first_prim_d1)
        first_prim_d1 <= 1;
      else
        first_prim_d1 <= 0;

      first_prim_d2  <= first_prim_d1;
      first_prim_d3  <= first_prim_d2;
      first_prim_d4  <= first_prim_d3;
      first_prim_d5  <= first_prim_d4;
      first_prim_d6  <= first_prim_d5;
      first_prim_d7  <= first_prim_d6;
      first_prim_d8  <= first_prim_d7;
      first_prim_d9  <= first_prim_d8;
      first_prim_d10 <= first_prim_d9;
      first_prim_d11 <= first_prim_d10;
      first_prim_dv  <= first_prim_d11;
  end

  initial
  begin
    qsim_en = 0;
    first_edge = 1;

    if ($getstr$plusarg("qsim_dump=", qsim) == 1)
    begin
      qsim_en = 1;
      qsim_chan = $fopen(qsim);

      $fwrite(qsim_chan,
	"#\n",
	"# RDP top-level tab file\n",
	"#\n");

      $fwrite(qsim_chan,
	"# Inputs\n",
	"dclk                  @DC 1(4) 0(4)\n",
	"clk                   @C 1(8) 0(8)\n",
	"gclk                  @I @E 0 @C dclk\n",
	"reset_l               @I @E 2 @C clk\n",
	"xbus_cs_data[63:0]    @I @E 2 @C clk\n",
	"xbus_cs_valid         @I @E 2 @C clk\n",
	"load_dv               @I @E 2 @C clk\n",
	"copy_load_dummy       @I @E 0 @C clk\n",
	"copy_load[63:0]       @B copy_load_oe 1 @E 5 @S 15 @C clk\n",
	"copy_load_oe          @O @S 15 @C clk\n",
	"mem_r[7:0]            @I @E 2 @C clk\n",
	"mem_g[7:0]            @I @E 2 @C clk\n",
	"mem_b[7:0]            @I @E 2 @C clk\n",
	"mem_a[2:0]            @I @E 2 @C clk\n",
	"mem_z[17:0]           @I @E 2 @C clk\n",
	"rel_sync_full         @I @E 2 @C clk\n",
	"flush                 @I @E 2 @C clk\n");

      $fwrite(qsim_chan,
	"# Outputs\n",
	"cs_xbus_req           @O @S 15 @C clk\n",
	"span_r[7:0]           @O @S 15 @C clk\n",
	"span_g[7:0]           @O @S 15 @C clk\n",
	"span_b[7:0]           @O @S 15 @C clk\n",
	"span_a[2:0]           @O @S 15 @C clk\n",
	"span_z[17:0]          @O @S 15 @C clk\n",
	"span_color_we         @O @S 15 @C clk\n",
	"span_depth_we         @O @S 15 @C clk\n",
	"strobe_sync_full      @O @S 15 @C clk\n",
	"ew_ms_length[11:0]    @O @S 15 @C clk @V first_prim_dv\n",
	"ew_ms_addr[19:0]      @O @S 15 @C clk @V first_prim_dv\n",
	"ew_ms_newspan         @O @S 15 @C clk @V first_prim_dv\n",
	"ew_ms_startspan       @O @S 15 @C clk @V first_prim_dv\n",
	"at_color_base[25:0]   @O @S 15 @C clk\n",
	"at_color_format[2:0]  @O @S 15 @C clk\n",
	"at_color_size[1:0]    @O @S 15 @C clk\n",
	"at_z_base[25:0]       @O @S 15 @C clk\n",
	"at_cycle_type[1:0]    @O @S 15 @C clk\n",
	"color_rmw             @O @S 15 @C clk\n",
	"at_z_rmw              @O @S 15 @C clk\n",
	"at_z_enable           @O @S 15 @C clk\n",
	"at_fill_color[31:0]   @O @S 15 @C clk\n",
	"tex_base[25:0]        @O @S 15 @C clk\n",
	"tex_width[9:0]        @O @S 15 @C clk\n",
	"tex_size[1:0]         @O @S 15 @C clk\n",
	"tex_format[2:0]       @O @S 15 @C clk\n",
	"ew_scissor_load       @O @S 15 @C clk\n",
	"tc_load               @O @S 15 @C clk\n",
	"load_tlut_en          @O @S 15 @C clk\n",
	"first_prim_dv         @V @C clk\n",
	"\n");	/* required newline */
    end
  end

  always @(clock)
  begin
    if(qsim_en && !first_edge)
    begin
      // write vector
      $fwrite(qsim_chan, 
	"%h ",   rdp_ms.gclk,
	"%h ",   rdp_ms.reset_l,
	"0x%h ", rdp_ms.xbus_cs_data,
	"%h ",   rdp_ms.xbus_cs_valid,
	"  ",
	"%h ",   rdp_ms.load_dv,
	"%h ",   ~rdp_ms.load_dv,
	"0x%h ", rdp_ms.copy_load,
	"%h ",   ~rdp_ms.load_dv,
	"  ",
	"0x%h ", rdp_ms.mem_r,
	"0x%h ", rdp_ms.mem_g,
	"0x%h ", rdp_ms.mem_b,
	"0x%h ", rdp_ms.mem_a,
	"0x%h ", rdp_ms.mem_z,
	"  ",
	"%h ",   rdp_ms.rel_sync_full,
	"%h ",   rdp_ms.flush,
	"    ",
	"%h ",   rdp_ms.cs_xbus_req,
	"  ",
	"0x%h ", rdp_ms.span_r,
	"0x%h ", rdp_ms.span_g,
	"0x%h ", rdp_ms.span_b,
	"0x%h ", rdp_ms.span_a,
	"0x%h ", rdp_ms.span_z,
	"%h ",   rdp_ms.span_color_we,
	"%h ",   rdp_ms.span_depth_we,
	"  ",
	"%h ",   rdp_ms.strobe_sync_full,
	"0x%h ", rdp_ms.ew_ms_length,
	"0x%h ", rdp_ms.ew_ms_addr,
	"%h ",   rdp_ms.ew_ms_newspan,
	"%h ",   rdp_ms.ew_ms_startspan,
	"  ",
	"0x%h ", rdp_ms.at_color_base,
	"0x%h ", rdp_ms.at_color_format,
	"0x%h ", rdp_ms.at_color_size,
	"  ",
	"0x%h ", rdp_ms.at_z_base,
	"0x%h ", rdp_ms.at_cycle_type,
	"%h ",   rdp_ms.color_rmw,
	"%h ",   rdp_ms.at_z_rmw,
	"%h ",   rdp_ms.at_z_enable,
	"0x%h ", rdp_ms.at_fill_color,
	"  ",
	"0x%h ", rdp_ms.tex_base,
	"0x%h ", rdp_ms.tex_width,
	"0x%h ", rdp_ms.tex_size,
	"0x%h ", rdp_ms.tex_format,
	"  ",
	"%h ",   rdp_ms.ew_scissor_load,
	"%h ",   rdp_ms.tc_load,
	"%h ",   rdp_ms.load_tlut_en,
	"%h ",   first_prim_dv,
	"\n");
    end
    else
      first_edge = 0;
  end


  //
  //  Qsim Tabular File for Edge Walker 
  //
  initial
  begin
    ew_qsim_en = 0;
    ew_first_edge = 1;

    if ($getstr$plusarg("ew_qsim_dump=", ew_qsim) == 1)
    begin
      ew_qsim_en = 1;
      ew_qsim_chan = $fopen(ew_qsim);

      $fwrite(ew_qsim_chan,
	"#\n",
	"# EW top-level tab file\n",
	"#\n");

      //
      //  Inputs that come from latches are clocked at
      //  2x since they change on the negative edge
      //
      $fwrite(ew_qsim_chan,
	"# Inputs\n",
	"dclk                  @DC 1(4) 0(4)\n",
	"clk                   @DC 1(8) 0(8)\n",
	"gclk                  @I @E 0 @C dclk\n",
	"cs_ew_d[63:0]         @I @E 2 @C clk\n",
	"cs_ew_newprim         @I @E 2 @C clk\n",
	"dxr[22:0]             @I @E 2 @C dclk\n",
	"dxg[22:0]             @I @E 2 @C dclk\n",
	"dxb[22:0]             @I @E 2 @C dclk\n",
	"dxa[22:0]             @I @E 2 @C dclk\n",
	"dxz[22:0]             @I @E 2 @C dclk\n",
	"dxs[22:0]             @I @E 2 @C dclk\n",
	"dxt[22:0]             @I @E 2 @C dclk\n",
	"dxw[22:0]             @I @E 2 @C dclk\n",
//	"dxl[22:0]             @I @E 2 @C dclk\n",
	"dyr[22:0]             @I @E 2 @C dclk\n",
	"dyg[22:0]             @I @E 2 @C dclk\n",
	"dyb[22:0]             @I @E 2 @C dclk\n",
	"dya[22:0]             @I @E 2 @C dclk\n",
	"dyz[22:0]             @I @E 2 @C dclk\n",
	"dys[22:0]             @I @E 2 @C dclk\n",
	"dyt[22:0]             @I @E 2 @C dclk\n",
	"dyw[22:0]             @I @E 2 @C dclk\n",
//	"dyl[22:0]             @I @E 2 @C dclk\n",
	"left_xmajor           @I @E 2 @C clk\n",
	"left_xminor           @I @E 2 @C clk\n",
	"left_offset           @I @E 2 @C clk\n",
	"sign_dxhdy_xmajor     @I @E 2 @C clk\n",
	"sign_dxhdy_offset     @I @E 2 @C clk\n",
	"width_cimage[9:0]     @I @E 2 @C dclk\n",
	"width_timage[9:0]     @I @E 2 @C dclk\n",
	"load_cmd_image        @I @E 2 @C dclk\n",
	"pixel_size[1:0]       @I @E 2 @C dclk\n",
	"texel_size[1:0]       @I @E 2 @C dclk\n",
	"cycle_type[1:0]       @I @E 2 @C dclk\n",
	"scbox_xmax[11:0]      @I @E 2 @C dclk\n",
	"scbox_xmin[11:0]      @I @E 2 @C dclk\n",
	"scbox_ymax[11:0]      @I @E 2 @C dclk\n",
	"scbox_ymin[11:0]      @I @E 2 @C dclk\n",
	"load_cmd_scissor      @I @E 2 @C clk\n",
	"load_cmd_ewstall      @I @E 2 @C clk\n",
	"load_cmd_offset       @I @E 2 @C clk\n",
	"load_cmd_tlut         @I @E 2 @C clk\n",
	"sc_field              @I @E 2 @C dclk\n",
	"odd_line              @I @E 2 @C dclk\n",
	"flush                 @I @E 2 @C clk\n",
	"reset_l               @I @E 2 @C clk\n");

      $fwrite(ew_qsim_chan,
	"# Outputs\n",
	"ew_cs_busy            @O @S 15 @C clk\n",
	"ew_cv_d[12:0]         @O @S 15 @C clk\n",
	"ew_cv_newspan         @O @S 15 @C clk\n",
	"ew_cv_start_x[11:0]   @O @S 15 @C clk\n",
	"ew_ms_length[11:0]    @O @S 15 @C clk @V first_prim_dv\n",
	"ew_ep_d[21:0]         @O @S 15 @C clk\n",
	"ew_ep_startspan       @O @S 15 @C clk\n",
	"ew_ms_addr[19:0]      @O @S 15 @C clk @V first_prim_dv\n",
	"first_prim_dv         @V @C clk\n",
	"\n");	/* required newline */
    end
  end

  always @(clock)
  begin
    if(ew_qsim_en && !ew_first_edge)
    begin
      // write vector
      $fwrite(ew_qsim_chan, 
	"%h ", rdp_ms.ew.gclk,
	"0x%h ", rdp_ms.ew.cs_ew_d[63:0],
	"%h ", rdp_ms.ew.cs_ew_newprim,
	"0x%h ", rdp_ms.ew.dxr[22:0],
	"0x%h ", rdp_ms.ew.dxg[22:0],
	"0x%h ", rdp_ms.ew.dxb[22:0],
	"0x%h ", rdp_ms.ew.dxa[22:0],
	"0x%h ", rdp_ms.ew.dxz[22:0],
	"0x%h ", rdp_ms.ew.dxs[22:0],
	"0x%h ", rdp_ms.ew.dxt[22:0],
	"0x%h ", rdp_ms.ew.dxw[22:0],
//	"0x%h ", rdp_ms.ew.dxl[22:0],
	"0x%h ", rdp_ms.ew.dyr[22:0],
	"0x%h ", rdp_ms.ew.dyg[22:0],
	"0x%h ", rdp_ms.ew.dyb[22:0],
	"0x%h ", rdp_ms.ew.dya[22:0],
	"0x%h ", rdp_ms.ew.dyz[22:0],
	"0x%h ", rdp_ms.ew.dys[22:0],
	"0x%h ", rdp_ms.ew.dyt[22:0],
	"0x%h ", rdp_ms.ew.dyw[22:0],
//	"0x%h ", rdp_ms.ew.dyl[22:0],
	"%h ", rdp_ms.ew.left_xmajor,
	"%h ", rdp_ms.ew.left_xminor,
	"%h ", rdp_ms.ew.left_offset,
	"%h ", rdp_ms.ew.sign_dxhdy_xmajor,
	"%h ", rdp_ms.ew.sign_dxhdy_offset,
	"0x%h ", rdp_ms.ew.width_cimage[9:0],
	"0x%h ", rdp_ms.ew.width_timage[9:0],
	"%h ", rdp_ms.ew.load_cmd_image,
	"0x%h ", rdp_ms.ew.pixel_size[1:0],
	"0x%h ", rdp_ms.ew.texel_size[1:0] ,
	"0x%h ", rdp_ms.ew.cycle_type[1:0] ,
	"0x%h ", rdp_ms.ew.scbox_xmax[11:0],
	"0x%h ", rdp_ms.ew.scbox_xmin[11:0],
	"0x%h ", rdp_ms.ew.scbox_ymax[11:0],
	"0x%h ", rdp_ms.ew.scbox_ymin[11:0],
	"%h ", rdp_ms.ew.load_cmd_scissor,
	"%h ", rdp_ms.ew.load_cmd_ewstall,
	"%h ", rdp_ms.ew.load_cmd_offset,
	"%h ", rdp_ms.ew.load_cmd_tlut,
	"%h ", rdp_ms.ew.sc_field,
	"%h ", rdp_ms.ew.odd_line,
	"%h ", rdp_ms.ew.flush,
	"%h ", rdp_ms.ew.reset_l,
	"    ",
	"%h ", rdp_ms.ew.ew_cs_busy,
	"0x%h ", rdp_ms.ew.ew_cv_d[12:0],
	"%h ", rdp_ms.ew.ew_cv_newspan,
	"0x%h ", rdp_ms.ew.ew_cv_start_x[11:0],
	"0x%h ", rdp_ms.ew.ew_ms_length[11:0],
	"0x%h ", rdp_ms.ew.ew_ep_d[21:0],
	"%h ", rdp_ms.ew.ew_ep_startspan,
	"0x%h ", rdp_ms.ew.ew_ms_addr[19:0],
	"%h ",   first_prim_dv,
	"\n");
    end
    else
      ew_first_edge = 0;
  end


// end include file