GNUmakefile
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#!smake -J 3
#
#
PRDEPTH = ../../../../..
include $(PRDEPTH)/PRdefs
CC=$(HOST_CC)
GCINCS=
GLDOPTS=
LCOPTS = -g
LVCSOPTS = -y . \
+incdir+$(PRDEPTH)/$(HW)/chip/rcp/inc
OLDOPTS = -y $(PRDEPTH)/$(HW)/chip/rcp/vi/src \
-y $(PRDEPTH)/$(HW)/chip/rcp/rdp/src \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/sc \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/ram \
-v $(PRDEPTH)/$(HW)/chip/lib/verilog/udp/compass_udps.v \
+libext+.v+.vzd \
-P $(ROOT)/PR/rdpsim/test/vi/OutData/vi_rand/Pli/pli.tab \
$(ROOT)/PR/rdpsim/test/vi/OutData/vi_rand/Pli/libpli.a \
RTLOPTS = -y $(PRDEPTH)/$(HW)/chip/rcp/vi/src \
-y $(PRDEPTH)/$(HW)/chip/rcp/rdp/src \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/ram \
+libext+.v \
-P $(ROOT)/PR/rdpsim/test/vi/OutData/vi_rand/Pli/pli.tab \
$(ROOT)/PR/rdpsim/test/vi/OutData/vi_rand/Pli/libpli.a \
SYNOPTS = -y $(PRDEPTH)/$(HW)/chip/rcp/vi/syn \
-y $(PRDEPTH)/$(HW)/chip/rcp/rdp/syn \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/$(HW)/chip/lib/verilog/ram \
+libext+.v+.vsyn \
-P $(ROOT)/PR/rdpsim/test/vi/OutData/vi_rand/Pli/pli.tab \
$(ROOT)/PR/rdpsim/test/vi/OutData/vi_rand/Pli/libpli.a \
LDIRT = driver*.v *.mem *.out vcs.log *.dump vi_rand0?? *.tab simv* inp??? Pli/*.o Pli/*.a checkrand rsimv* ssimv* rtlcsrc* syncsrc*
SUBDIRS = Pli
HDR = $(ROOT)/PR/include
LCINCS = -I. \
-I$(HDR) \
-I$(ROOT)
include $(PRDEPTH)/PRrules
.mem.out:
ERROR = \
@if grep "ERROR" FILE ; \
then echo ""; \
else \
echo "NO ERRORS IN SIMULATION"; \
fi
RTESTS = rsimv000
STESTS = ssimv000
OTESTS = simv000
default rtests: checkrand $(RTESTS)
stests: $(STESTS)
otests: $(OTESTS)
$(PLI)/libpli.a: $(_FORCE)
(cd Pli; make ; cd ..)
checkrand: checkrand.c vi_rand.c
$(CC) $(LCINCS) $(LCOPTS) -o $@ checkrand.c -lm
inp000: inp000.c
$(CC) $(LCINCS) -o $@ $?
vi_rand000.tab: inp000
./inp000 > vi_rand000.tab
driver000.v: vi_rand000.tab $(TAB2VMEM)
$(TAB2VMEM) -o /dev/null -s 100 vi_rand000.tab > driver000.v
simv000: top_level.v driver000.v display.v vi_rand000.mem $(PLI)/libpli.a checkrand
$(VCS) $(VCSOPTS) $(OLDOPTS) -o simv000 -Mdir="vi_rand000" top_level.v driver000.v
@ if [ "$(DUMP)" ]; \
then (echo "simv -dump" ; ./simv000 -vcd verilog000.dump +out=test000.out +dump=yes +mem=vi_rand000.mem > simv000.out) \
else (echo "simv -nodump" ; ./simv000 +mem=vi_rand000.mem +out=test000.out +vcs+dumpvarsoff > simv000.out) \
fi
./checkrand test000.out | tee checkrand000.out
$(ERROR:FILE=checkrand000.out)
rsimv000: top_level.v driver000.v display.v vi_rand000.mem $(PLI)/libpli.a checkrand
$(VCS) $(VCSOPTS) $(RTLOPTS) -o rsimv000 -Mdir="rtlcsrc000" top_level.v driver000.v
@ if [ "$(DUMP)" ]; \
then (echo "rsimv -dump" ; ./rsimv000 -vcd rverilog000.dump +out=rtest000.out +dump=yes +mem=vi_rand000.mem > rsimv000.out) \
else (echo "rsimv -nodump" ; ./rsimv000 +mem=vi_rand000.mem +out=rtest000.out +vcs+dumpvarsoff > rsimv000.out) \
fi
./checkrand rtest000.out | tee rcheckrand000.out
$(ERROR:FILE=rcheckrand000.out)
ssimv000: top_level.v driver000.v display.v vi_rand000.mem $(PLI)/libpli.a checkrand
$(VCS) $(VCSOPTS) $(SYNOPTS) -o ssimv000 -Mdir="syncsrc000" top_level.v driver000.v
@ if [ "$(DUMP)" ]; \
then (echo "ssimv -dump" ; ./ssimv000 -vcd sverilog000.dump +out=stest000.out +dump=yes +mem=vi_rand000.mem > ssimv000.out) \
else (echo "ssimv -nodump" ; ./ssimv000 +mem=vi_rand000.mem +out=stest000.out +vcs+dumpvarsoff > ssimv000.out) \
fi
./checkrand stest000.out | tee scheckrand000.out
$(ERROR:FILE=scheckrand000.out)