#!smake
#
#  This makefile has rules for making both the executables
#  which make up the simulator, and for running test cases.
#
# $Revision: 1.1.1.1 $
#
COMMONPREF=cc
PRDEPTH = ../../..
include $(PRDEPTH)/PRdefs

#
#  Directories
#
SIMLIB		= ../../simlib
SRC    		= ../../src
HDR    		= ../../hdr
WIR    		= Wir
INDATA 		= InData
OUTDATA		= OutData
QSIM            = qsim
HW           = $(PRDEPTH)/hw/chip/rcp
HWLIB        = $(PRDEPTH)/hw/chip/lib/verilog

SUBDIRS		= $(WIR)

#
#		Look in $(SRC) directory for C-sim source
#
.PATH:		$(SRC)

#
#  C Sources
#
TEST_FILES 	= \
        	$(SRC)/bl.c \
		expand.c \
        	driver.c \
        	bl_test_0.c

#
#  Object Files
#
TEST_OBJ 	= $(TEST_FILES:.c=.o)
TEST_OBJS    	= $(TEST_OBJ:T)

#
#  Header file Directories
#
LCINCS 		= -I. \
	 	-I$(SIMLIB) \
	 	-I$(HDR)

GCINCS 		=

#
# Compiler options
#
OPTIMIZER	= -g
LCOPTS		= -fullwarn

#
#  Linker Directories and Options
# 
LLDOPTS 	= -L. -L$(SIMLIB)
GLDOPTS 	=
LLDLIBS 	= -lsimlib

#
#  Verilog compiler options
#

RTLOPTS =	-y $(HW)/bl/src \
		-y $(HWLIB)/stdcell \
		-y $(HWLIB)/ram \
		-v $(HWLIB)/udp/compass_udps.v \
		+libext+.v+.vzd \
		-Mdir=rtlcsrc


SYNOPTS =	-y $(HW)/bl/syn \
		-y $(HWLIB)/stdcell \
		-y $(HWLIB)/ram \
		-v $(HWLIB)/udp/compass_udps.v \
		+libext+.v+.vzd+.vsyn \
		-Mdir=syncsrc

#
#  Default Targets
#
RTESTS 	= rtest002 

STESTS 	= stest002 

QTESTS  = qtest002

LDIRT  	= rsimv rsimv.daidb driver.v csrc verilog.dump bl_test bl_test_0.c \
	  $(INDATA)/inp*.tab $(OUTDATA)/test*.tab test*.mem \
	  fast*.out fast*.merge \
	  ${QSIM}/*.tab ${QSIM}/*.sim* ${QSIM}/*.trc* ${QSIM}/*.simlog*

default install: $(RTESTS)

stests: $(STESTS)

qtests: $(QTESTS)

$(COMMONTARGS): $(COMMONPREF)$$@
	$(SUBDIRS_MAKERULE)

#
#  SGI/Project Reality Common Rules
#
include $(PRDEPTH)/PRrules

#
#  Use HOST compile
#
.c.o:
	$(HOST_CC) $(CFLAGS) -c $*.c

#
#  Target for creating all .1 files, Viewlogic netlists
#
$(WIR)/bl_test.1: $(_FORCE)
	cd $(WIR); $(MAKE)

###############################################################################
#
#  Compile 'C' processes
#
bl_test_0.c: $(WIR)/bl_test.1 bl_test.config $(XNET)
	$(XNET) -d $(WIR) bl_test -c bl_test.config

bl_test: bl_test_0.c $(SIMLIB) $(TEST_OBJS)
	$(HOST_CC) $(CFLAGS) $(TEST_OBJS) $(LDFLAGS) -o $@


###############################################################################
#
# Compile Verilog processes
#

driver.v: $(OUTDATA)/bl_all/test002.tab $(TAB2VMEM)
	$(TAB2VMEM) -o /dev/null -s 100 $(OUTDATA)/bl_all/test002.tab > driver.v

rsimv: top_level.v driver.v $(_FORCE)
	$(VCS) $(VCSOPTS) $(RTLOPTS) top_level.v driver.v -o $@

ssimv: top_level.v driver.v $(_FORCE)
	$(VCS) $(VCSOPTS) $(SYNOPTS) top_level.v driver.v -o $@


###############################################################################
#
#  Test Targets
#

#
# test001  This is a generic test.  test001 uses inp0001.tab and creates 
#              bl_all001.tab.   These files are often overwritten so
#              don't use 001 (test001 or inp001 or etc) for any permanent
#              tests
#
rtest001: rsimv $(OUTDATA)/bl_all/test001.tab
	rsimv +mem=$(?:S/rsimv//) > $*.out
	$(LOG_RESULT)

stest001: ssimv $(OUTDATA)/bl_all/test001.tab
	rsimv +mem=$(?:S/ssimv//) > $*.out
	$(LOG_RESULT)

#
# test002  Test the 20 rendering modes.  Each rendering mode it tested
#              with a variety of pixel coverages and alphas and a variety
#              of memory coverages.  Each rendering mode, pixel coverage,
#              pixel alpha, memory coverage case is tested with 6 different
#              cases of the Z test.
#
rtest002: rsimv $(OUTDATA)/bl_all/test002.mem
	rsimv +mem=$(?:S/rsimv//) > $*.out
	$(LOG_RESULT)

stest002: ssimv $(OUTDATA)/bl_all/test002.mem
	ssimv +mem=$(?:S/ssimv//) > $*.out
	$(LOG_RESULT)

qtest002: $(_FORCE)
	(cd qsim; make test002.trc)

###############################################################################
#
# Input tab file rules
#

#
# test001
#
# There is no rule to make inp001.tab.  The inp001.tab file should be copied
# to $(INDATA) before this is run.

#
# test002
#
$(INDATA)/inp002.tab: $(INDATA)/inp002.c
	$(HOST_CC) -o $(INDATA)/inp002 $(INDATA)/inp002.c
	cat $(INDATA)/SignalNames.tab > $(INDATA)/inp002.tab
	$(INDATA)/inp002 -z >> $(INDATA)/inp002.tab

###############################################################################
#
# Output tab file rules
#

#
# test001
#
$(OUTDATA)/bl_all/test001.tab: bl_test $(INDATA)/inp001.tab
	bl_test -i 1 -o bl_all > $(OUTDATA)/bl_all/test001.tab

#
# test002
#
$(OUTDATA)/bl_all/test002.tab: bl_test $(INDATA)/inp002.tab \
			       $(OUTDATA)/bl_all/test002.tab.base
	bl_test -i 2 -o bl_all > $(OUTDATA)/bl_all/test002.tab
	cmp -s $@ $@.base

###############################################################################
#
#  "Fast" rules for private use
#

.tabo.memo:
	$(TAB2VMEM) -o $*.memo -s 100 $*.tabo > /dev/null

#fast001: $(OUTDATA)/bl_all/test001.mem
#	rsimv +mem=$? | tee $*.out
#	$(MERRG) $(OUTDATA)/bl_all/test001.tab $*.out > $*.merge

fast001: $(OUTDATA)/bl_all/test001.memo
	rsimv +mem=$(OUTDATA)/bl_all/test001.memo | tee $*.out
	$(MERRG) $(OUTDATA)/bl_all/test001.tabo $*.out > $*.merge

fast002: $(OUTDATA)/bl_all/test002.mem
	rsimv +mem=$? | tee $*.out
	$(MERRG) $(OUTDATA)/bl_all/test002.tab $*.out > $*.merge