#!smake
#
#  This makefile has rules for making both the executables
#  which make up the simulator, and for running test cases.
#
# $Revision: 1.1.1.1 $
#
COMMONPREF=cv
PRDEPTH = ../../..

include $(PRDEPTH)/PRdefs

#
#  Directories
#
SIMLIB		= ../../simlib
SRC    		= ../../src
HDR    		= ../../hdr
WIR    		= Wir
INDATA 		= InData
OUTDATA		= OutData
HW		= $(PRDEPTH)/hw/chip/rcp
HWLIB		= $(PRDEPTH)/hw/chip/lib/verilog
QSIM            = qsim

#
#  Subdirectories
#
SUBDIRS		= $(WIR)

#
#		Look in $(SRC) directory for C-sim source
#
.PATH:		$(SRC)

#
#  C Sources
#
TEST_FILES 	= \
        	$(SRC)/cv.c \
		expand.c \
		driver.c \
        	cv_test_0.c

#
#  Object Files
#
TEST_OBJ 	= ${TEST_FILES:.c=.o}
TEST_OBJS    	= ${TEST_OBJ:T}

#
#  Header file Directories
#
LCINCS 		= -g -I. \
	 	-I$(SIMLIB) \
	 	-I$(HDR)

GCINCS 		=

#
#  Linker Directories and Options
# 
LLDOPTS 	= -L. -L$(SIMLIB) -lm
GLDOPTS 	=
LLDLIBS 	= -lsimlib -lm

#
#  Verilog compiler options
#
LVCSOPTS = +incdir+$(HW)/inc

RTLOPTS =  -y $(HW)/cv/src \
	   -y $(HW)/rdp/src \
	   -y $(HWLIB)/stdcell \
	   -y $(HWLIB)/ram \
	   -v $(HWLIB)/udp/compass_udps.v \
	   +libext+.v+.vzd \
	   -Mdir=rtlcsrc

SYNOPTS  = -y $(HW)/cv/syn \
	   -y $(HW)/rdp/src \
	   -y $(HWLIB)/stdcell \
	   -y $(HWLIB)/ram \
	   -v $(HWLIB)/udp/compass_udps.v \
	   +libext+.v+.vsyn \
	   -Mdir=syncsrc

#DUMP	= +dump

#
#  Test Targets
#
RTESTS 	= rtest000 rtest001 rtest002 rtest003

STESTS 	= stest000 stest001 stest002 stest003

QTESTS  = qtest000 qtest001 qtest002 qtest003

FAST 	= fast000 fast001 fast002 fast003

LDIRT  	= cv_test_0.c dump *.tab ${QSIM}/*.tab ${QSIM}/*.sim* ${QSIM}/*.trc* ${QSIM}/*.simlog*

#
#  SGI Common Rules
#
include $(PRDEPTH)/PRrules

#
#  Use HOST compile
#
.c.o:
	$(HOST_CC) $(CFLAGS) -c $*.c

default rtests: $(RTESTS)

stests: $(STESTS)

qtests: $(QTESTS)

fast: $(FAST)
	
$(COMMONTARGS): $(COMMONPREF)$$@
	$(SUBDIRS_MAKERULE)

#
#  Target for creating .1 files, Viewlogic Netlists
#
$(WIR)/cv_test.1: $(FORCE)
	cd $(WIR); $(MAKE)

#
#  Compile 'C' processes
#
cv_test_0.c: $(WIR)/cv_test.1 cv_test.config $(XNET)
	$(XNET) -d $(WIR) cv_test -c cv_test.config

cv_test: $(TEST_OBJS)
	$(HOST_CC) $(TEST_OBJS) $(LDFLAGS) -o $@

#
# Compile Verilog processes
#

driver.v: $(OUTDATA)/cv_all/test000.tab $(TAB2VMEM)
	$(TAB2VMEM) -o /dev/null -s 100 $(OUTDATA)/cv_all/test000.tab > driver.v

rsimv: top_level.v driver.v $(_FORCE)
	$(VCS) $(VCSOPTS) $(RTLOPTS) top_level.v driver.v -o $@

ssimv: top_level.v driver.v $(_FORCE)
	$(VCS) $(VCSOPTS) $(SYNOPTS) top_level.v driver.v -o $@

#
#  Test Rules
#

#
# test000  Sanity Check, run a few simple vectors through to check for
# test000  gross or even pretty errors.
#
rtest000: rsimv $(OUTDATA)/cv_all/test000.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest000: ssimv $(OUTDATA)/cv_all/test000.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

qtest000: $(_FORCE)
	(cd qsim; make test000.trc)

fast000: $(OUTDATA)/cv_all/test000.mem
	rsimv +mem=$? > $*.out
	$(LOG_ERROR)

$(OUTDATA)/cv_all/test000.tab: cv_test $(INDATA)/inp000.tab \
			       $(OUTDATA)/cv_all/test000.tab.base
	./cv_test -i 0 -o cv_all -t 0
	cmp -s $@ $@.base

#
# test001  Two fairly shallow edges, look at offsets
#
rtest001: rsimv $(OUTDATA)/cv_all/test001.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest001: ssimv $(OUTDATA)/cv_all/test001.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_ERROR)

qtest001: $(_FORCE)
	(cd qsim; make test001.trc)

fast001: $(OUTDATA)/cv_all/test001.mem
	rsimv +mem=$? > $*.out
	$(LOG_ERROR)

$(OUTDATA)/cv_all/test001.tab: cv_test $(INDATA)/inp001.tab \
			       $(OUTDATA)/cv_all/test001.tab.base
	./cv_test -i 1 -o cv_all -t 1
	cmp -s $@ $@.base

#
# test002  Random test cases
#
rtest002: rsimv $(OUTDATA)/cv_all/test002.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest002: ssimv $(OUTDATA)/cv_all/test002.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_ERROR)

qtest002: $(_FORCE)
	(cd qsim; make test002.trc)

fast002: $(OUTDATA)/cv_all/test002.mem
	rsimv +mem=$? > $*.out
	$(LOG_ERROR)

$(OUTDATA)/cv_all/test002.tab: cv_test $(INDATA)/inp002.tab \
			       $(OUTDATA)/cv_all/test002.tab.base
	./cv_test -i 2 -o cv_all -t 2
	cmp -s $@ $@.base

#
# test003  Random test cases with random left/right and cycle_mode
#
rtest003: rsimv $(OUTDATA)/cv_all/test003.mem
	rsimv +mem=$(?:S/rsimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

stest003: ssimv $(OUTDATA)/cv_all/test003.mem
	ssimv +mem=$(?:S/ssimv//) $(DUMP) > $*.out
	$(LOG_RESULT)

qtest003: $(_FORCE)
	(cd qsim; make test003.trc)

fast003: $(OUTDATA)/cv_all/test003.mem
	rsimv +mem=$? > $*.out
	$(LOG_ERROR)

$(OUTDATA)/cv_all/test003.tab: cv_test $(INDATA)/inp003.tab \
			       $(OUTDATA)/cv_all/test003.tab.base
	./cv_test -i 3 -o cv_all -t 3
	cmp -s $@ $@.base