top_level.v
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/**************************************************************************
* *
* Copyright (C) 1994, Silicon Graphics, Inc. *
* *
* These coded instructions, statements, and computer programs contain *
* unpublished proprietary information of Silicon Graphics, Inc., and *
* are protected by Federal copyright law. They may not be disclosed *
* to third parties or copied or duplicated in any form, in whole or *
* in part, without the prior written consent of Silicon Graphics, Inc. *
* *
*************************************************************************/
// $Id: top_level.v,v 1.1.1.1 2002/05/02 03:29:06 blythe Exp $
////////////////////////////////////////////////////////////////////////
//
// Project Reality
//
// module: top_level
// description: Top Level Driver
//
// designer: Tony DeLaurier
// date: 10/25/94
//
////////////////////////////////////////////////////////////////////////
`timescale 10ps / 10ps //1unit = 0.01ns
module top_level();
// bist inputs
wire clk;
wire reset_l;
wire bist_go;
wire bist_check;
wire [1:0] sys_addr;
wire [15:0] sys_din;
wire sys_web;
// bist outputs
// instance driver
driver driver(.clk(clk), .reset_l(reset_l), .bist_go(bist_go),
.bist_check(bist_check), .sys_addr(sys_addr), .sys_din(sys_din), .sys_web(sys_web));
// instance bist
ram_bist_tmem bist (.clk(clk), .reset_l(reset_l), .bist_go(bist_go),
.bist_check(bist_check), .sys_addr(sys_addr), .sys_din(sys_din),
.sys_web(sys_web));
// kill simulation when tabular file read
always @(driver.EndVectors)
$finish;
// dump file
initial
begin
$dumpvars;
end
endmodule // top_level