Makefile
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#!smake -J 5
PRDEPTH = ../../../../..
include $(PRDEPTH)/PRdefs
LVCSOPTS = -y . \
-y $(PRDEPTH)/hw/chip/rcp/tc/src \
-y $(PRDEPTH)/hw/chip/rcp/tm/src \
-y $(PRDEPTH)/hw/chip/rcp/su/src \
-y $(PRDEPTH)/hw/chip/rcp/rdp/src \
-y $(PRDEPTH)/hw/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/hw/chip/lib/verilog/ram \
-v $(PRDEPTH)/hw/chip/lib/verilog/udp/compass_udps.v \
+libext+.v+.vzd \
+incdir+$(PRDEPTH)/hw/chip/rcp/inc
LDIRT = driver*.v *.mem *.out vcs.log *.dump simv*
TESTS = bist000 bist001 bist002
FAST = fast000 fast001 fast002
ERROR = \
@if grep "ERROR IN SIMULATION" FILE ; \
then \
echo ""; \
else \
echo "NO ERRORS IN SIMULATION"; \
fi
default: $(TESTS)
include $(PRDEPTH)/PRrules
.mem.out:
$(TESTS): simv000 simv001 simv002
driver000.v: bist000.tab $(TAB2VMEM)
$(TAB2VMEM) -o /dev/null -s 100 bist000.tab > driver000.v
driver001.v: bist001.tab $(TAB2VMEM)
$(TAB2VMEM) -o /dev/null -s 100 bist001.tab > driver001.v
driver002.v: bist002.tab $(TAB2VMEM)
$(TAB2VMEM) -o /dev/null -s 100 bist002.tab > driver002.v
simv000: top_level.v driver000.v bist000.mem $(_FORCE)
$(VCS) $(VCSOPTS) -o simv000 -Mdir="bist000" top_level.v driver000.v
@ if [ "$(DUMP)" ]; \
then (echo "simv000 +mem=bist000.mem > simv000.out"; simv000 -vcd /hosts/baraka/var/tmp/tonyd/verilog000.dump +mem=bist000.mem > simv000.out;) \
else \
(echo "simv000 +mem=bist000.mem > simv000.out"; simv000 +mem=bist000.mem +vcs+dumpvarsoff > simv000.out;) \
fi
$(ERROR:FILE=simv000.out)
$(LOG_ERROR)
simv001: top_level.v driver001.v bist001.mem $(_FORCE)
$(VCS) $(VCSOPTS) -o simv001 -Mdir="bist001" top_level.v driver001.v
@ if [ "$(DUMP)" ]; \
then (echo "simv001 +mem=bist001.mem > simv001.out"; simv001 -vcd verilog001.dump +mem=bist001.mem > simv001.out;) \
else \
(echo "simv001 +mem=bist001.mem > simv001.out"; simv001 +mem=bist001.mem +vcs+dumpvarsoff > simv001.out;) \
fi
$(ERROR:FILE=simv001.out)
$(LOG_ERROR)
simv002: top_level.v driver002.v bist002.mem $(_FORCE)
$(VCS) $(VCSOPTS) -o simv002 -Mdir="bist002" top_level.v driver002.v
@ if [ "$(DUMP)" ]; \
then (echo "simv002 +mem=bist002.mem > simv002.out"; simv002 -vcd verilog002.dump +mem=bist002.mem > simv002.out;) \
else \
(echo "simv002 +mem=bist002.mem > simv002.out"; simv002 +mem=bist002.mem +vcs+dumpvarsoff > simv002.out;) \
fi
$(ERROR:FILE=simv002.out)
$(LOG_ERROR)
fast: $(FAST)
fast000: bist000.mem
simv000 +mem=$? | tee $*.out
fast001: bist001.mem
simv001 +mem=$? | tee $*.out
fast002: bist002.mem
simv002 +mem=$? | tee $*.out