Makefile
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#!smake -J 5
PRDEPTH = ../../../../..
include $(PRDEPTH)/PRdefs
#
# Directories
#
TCTM = ../..
INDATA = ../../InData
RTLOPTS = -y ../../fixture/src \
-y $(PRDEPTH)/hw/chip/rcp/tc/src \
-y $(PRDEPTH)/hw/chip/rcp/tm/src \
-y $(PRDEPTH)/hw/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/hw/chip/lib/verilog/ram \
+libext+.v+.vzd \
+incdir+$(PRDEPTH)/hw/chip/rcp/inc
SYNOPTS = -y ../../fixture/src \
-y $(PRDEPTH)/hw/chip/rcp/tc/syn \
-y $(PRDEPTH)/hw/chip/rcp/tm/syn \
-y $(PRDEPTH)/hw/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/hw/chip/lib/verilog/ram \
+libext+.v+.vzd+.vsyn
LDIRT = driver*.v *.mem *.out vcs.log *.dump $(TMPDIR)/$(USER)_tc_div016 $(TMPDIR)/$(USER)_tc_div016_syn *.tab simv*
RTESTS = tc_div016
STESTS = tc_div016_syn
FAST = fast016
ERROR = \
@if grep "ERROR IN SIMULATION" FILE ; \
then \
echo ""; \
else \
echo "NO ERRORS IN SIMULATION"; \
fi
default: $(RTESTS)
stests: $(STESTS)
include $(PRDEPTH)/PRrules
.mem.out:
$(RTESTS): simv016
$(STESTS): simv016_syn
tc_div016.tab: $(TCTM)/tctm $(INDATA)/inp015.tab $(INDATA)/inp006.tab $(INDATA)/inp014.tab $@.base.Z
(cd ../..; make test016)
/usr/bsd/uncompress $@.base.Z
cmp $@ $@.base
/usr/bsd/compress $@.base
driver016.v: tc_div016.tab $(TAB2VMEM)
$(TAB2VMEM) -o /dev/null -s 100 tc_div016.tab > driver016.v
simv016: top_level.v driver016.v tc_div016.mem $(_FORCE)
$(VCS) $(VCSOPTS) $(RTLOPTS) -o simv016 -Mdir="$(TMPDIR)/$(USER)_tc_div016" top_level.v driver016.v
@ if [ "$(DUMP)" ]; \
then \
(echo "simv016 +mem=tc_div016.mem > simv016.out"; simv016 -vcd verilog016.dump +mem=tc_div016.mem > simv016.out;) \
else \
(echo "simv016 +mem=tc_div016.mem > simv016.out"; simv016 +mem=tc_div016.mem +vcs+dumpvarsoff > simv016.out;) \
fi
$(ERROR:FILE=simv016.out)
$(LOG_ERROR)
simv016_syn: top_level.vsyn driver016.v tc_div016.mem $(_FORCE)
VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so \
$(VCS) $(VCSOPTS) $(SYNOPTS) -o $@ \
-Mdir="$(TMPDIR)/$(USER)_tc_div016_syn" \
top_level.vsyn driver016.v
@ if [ "$(DUMP)" ]; \
then \
(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tc_div016.mem > $@.out"; $@ -vcd verilog016_syn.dump +mem=tc_div016.mem > $@.out;) \
else \
(LD_LIBRARY_PATH=$(VCSDIR)/lib echo "$@ +mem=tc_div016.mem > $@.out"; $@ +mem=tc_div016.mem +vcs+dumpvarsoff > $@.out;) \
fi
$(ERROR:FILE=simv016_syn.out)
$(LOG_ERROR)
fast: $(FAST)
fast016: tc_div016.mem
simv016 +mem=$? | tee $*.out