test004.v
8.54 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
//
// test004 Perform odd-byte transfer sizes and address offsets for
// DMA writes
//
reg [(DBUS_DATA_SIZE*2)-1:0] test004_expected_d_mem [0:55];
reg [(EBUS_DATA_SIZE*2)-1:0] test004_expected_e_mem [0:55];
task test004;
reg [CBUS_DATA_SIZE-1:0] address;
reg [DBUS_DATA_SIZE-1:0] actual_d_data [0:1], expected_d_data [0:1];
reg [EBUS_DATA_SIZE-1:0] actual_e_data [0:1], expected_e_data [0:1];
integer num_bytes, offset, index;
begin
test004_initialize;
address = 0;
for (num_bytes = 1; num_bytes < 8; num_bytes = num_bytes + 1)
begin
for (offset = 0; offset < 8; offset = offset + 1)
begin
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, address, BUS_DEVICE_MI, -2, 16);
while (!dma_start)
@(posedge clock);
dbus_data_out <= 64'hffffffff_ffffffff;
ebus_data_out <= 8'hff;
@(posedge clock);
address = address + 16;
end
end
address = 0;
for (num_bytes = 1; num_bytes < 8; num_bytes = num_bytes + 1)
begin
for (offset = 0; offset < 8; offset = offset + 1)
begin
cbus_dma_write(`DMA_UNMASKED, `DMA_UP, address + offset,
BUS_DEVICE_MI, -2, num_bytes + offset);
dbus_put_data(64'h00000000_00000000, 8'h00, -2);
address = address + 16;
end
end
address = 0;
index = 0;
for (num_bytes = 1; num_bytes < 8; num_bytes = num_bytes + 1)
begin
for (offset = 0; offset < 8; offset = offset + 1)
begin
{ expected_d_data[0], expected_d_data[1] } =
test004_expected_d_mem[index];
{ expected_e_data[0], expected_e_data[1] } =
test004_expected_e_mem[index];
cbus_dma_read(`DMA_NOSUBBLOCK, `DMA_UP, address, BUS_DEVICE_MI, 3, 16);
while (!dma_start)
@(posedge clock);
check_data("test004", expected_d_data[0], dbus_data_reg,
expected_e_data[0], ebus_data_reg);
@(posedge clock);
check_data("test004", expected_d_data[1], dbus_data_reg,
expected_e_data[1], ebus_data_reg);
if (!dma_last)
begin
$write("test004: dma_last expected: %d was %d at time %d\n",
1'b1, dma_last, $time);
errors = errors + 1;
end
address = address + 16;
index = index + 1;
end
end
end
endtask
task test004_initialize;
begin
test004_expected_d_mem[00] = 128'h00ffffffffffffff_ffffffffffffffff;
test004_expected_d_mem[01] = 128'hff00ffffffffffff_ffffffffffffffff;
test004_expected_d_mem[02] = 128'hffff00ffffffffff_ffffffffffffffff;
test004_expected_d_mem[03] = 128'hffffff00ffffffff_ffffffffffffffff;
test004_expected_d_mem[04] = 128'hffffffff00ffffff_ffffffffffffffff;
test004_expected_d_mem[05] = 128'hffffffffff00ffff_ffffffffffffffff;
test004_expected_d_mem[06] = 128'hffffffffffff00ff_ffffffffffffffff;
test004_expected_d_mem[07] = 128'hffffffffffffff00_ffffffffffffffff;
test004_expected_d_mem[08] = 128'h0000ffffffffffff_ffffffffffffffff;
test004_expected_d_mem[09] = 128'hff0000ffffffffff_ffffffffffffffff;
test004_expected_d_mem[10] = 128'hffff0000ffffffff_ffffffffffffffff;
test004_expected_d_mem[11] = 128'hffffff0000ffffff_ffffffffffffffff;
test004_expected_d_mem[12] = 128'hffffffff0000ffff_ffffffffffffffff;
test004_expected_d_mem[13] = 128'hffffffffff0000ff_ffffffffffffffff;
test004_expected_d_mem[14] = 128'hffffffffffff0000_ffffffffffffffff;
test004_expected_d_mem[15] = 128'hffffffffffffff00_00ffffffffffffff;
test004_expected_d_mem[16] = 128'h000000ffffffffff_ffffffffffffffff;
test004_expected_d_mem[17] = 128'hff000000ffffffff_ffffffffffffffff;
test004_expected_d_mem[18] = 128'hffff000000ffffff_ffffffffffffffff;
test004_expected_d_mem[19] = 128'hffffff000000ffff_ffffffffffffffff;
test004_expected_d_mem[20] = 128'hffffffff000000ff_ffffffffffffffff;
test004_expected_d_mem[21] = 128'hffffffffff000000_ffffffffffffffff;
test004_expected_d_mem[22] = 128'hffffffffffff0000_00ffffffffffffff;
test004_expected_d_mem[23] = 128'hffffffffffffff00_0000ffffffffffff;
test004_expected_d_mem[24] = 128'h00000000ffffffff_ffffffffffffffff;
test004_expected_d_mem[25] = 128'hff00000000ffffff_ffffffffffffffff;
test004_expected_d_mem[26] = 128'hffff00000000ffff_ffffffffffffffff;
test004_expected_d_mem[27] = 128'hffffff00000000ff_ffffffffffffffff;
test004_expected_d_mem[28] = 128'hffffffff00000000_ffffffffffffffff;
test004_expected_d_mem[29] = 128'hffffffffff000000_00ffffffffffffff;
test004_expected_d_mem[30] = 128'hffffffffffff0000_0000ffffffffffff;
test004_expected_d_mem[31] = 128'hffffffffffffff00_000000ffffffffff;
test004_expected_d_mem[32] = 128'h0000000000ffffff_ffffffffffffffff;
test004_expected_d_mem[33] = 128'hff0000000000ffff_ffffffffffffffff;
test004_expected_d_mem[34] = 128'hffff0000000000ff_ffffffffffffffff;
test004_expected_d_mem[35] = 128'hffffff0000000000_ffffffffffffffff;
test004_expected_d_mem[36] = 128'hffffffff00000000_00ffffffffffffff;
test004_expected_d_mem[37] = 128'hffffffffff000000_0000ffffffffffff;
test004_expected_d_mem[38] = 128'hffffffffffff0000_000000ffffffffff;
test004_expected_d_mem[39] = 128'hffffffffffffff00_00000000ffffffff;
test004_expected_d_mem[40] = 128'h000000000000ffff_ffffffffffffffff;
test004_expected_d_mem[41] = 128'hff000000000000ff_ffffffffffffffff;
test004_expected_d_mem[42] = 128'hffff000000000000_ffffffffffffffff;
test004_expected_d_mem[43] = 128'hffffff0000000000_00ffffffffffffff;
test004_expected_d_mem[44] = 128'hffffffff00000000_0000ffffffffffff;
test004_expected_d_mem[45] = 128'hffffffffff000000_000000ffffffffff;
test004_expected_d_mem[46] = 128'hffffffffffff0000_00000000ffffffff;
test004_expected_d_mem[47] = 128'hffffffffffffff00_0000000000ffffff;
test004_expected_d_mem[48] = 128'h00000000000000ff_ffffffffffffffff;
test004_expected_d_mem[49] = 128'hff00000000000000_ffffffffffffffff;
test004_expected_d_mem[50] = 128'hffff000000000000_00ffffffffffffff;
test004_expected_d_mem[51] = 128'hffffff0000000000_0000ffffffffffff;
test004_expected_d_mem[52] = 128'hffffffff00000000_000000ffffffffff;
test004_expected_d_mem[53] = 128'hffffffffff000000_00000000ffffffff;
test004_expected_d_mem[54] = 128'hffffffffffff0000_0000000000ffffff;
test004_expected_d_mem[55] = 128'hffffffffffffff00_000000000000ffff;
test004_expected_e_mem[00] = 16'h7f_ff;
test004_expected_e_mem[01] = 16'hbf_ff;
test004_expected_e_mem[02] = 16'hdf_ff;
test004_expected_e_mem[03] = 16'hef_ff;
test004_expected_e_mem[04] = 16'hf7_ff;
test004_expected_e_mem[05] = 16'hfb_ff;
test004_expected_e_mem[06] = 16'hfd_ff;
test004_expected_e_mem[07] = 16'hfe_ff;
test004_expected_e_mem[08] = 16'h3f_ff;
test004_expected_e_mem[09] = 16'h9f_ff;
test004_expected_e_mem[10] = 16'hcf_ff;
test004_expected_e_mem[11] = 16'he7_ff;
test004_expected_e_mem[12] = 16'hf3_ff;
test004_expected_e_mem[13] = 16'hf9_ff;
test004_expected_e_mem[14] = 16'hfc_ff;
test004_expected_e_mem[15] = 16'hfe_7f;
test004_expected_e_mem[16] = 16'h1f_ff;
test004_expected_e_mem[17] = 16'h8f_ff;
test004_expected_e_mem[18] = 16'hc7_ff;
test004_expected_e_mem[19] = 16'he3_ff;
test004_expected_e_mem[20] = 16'hf1_ff;
test004_expected_e_mem[21] = 16'hf8_ff;
test004_expected_e_mem[22] = 16'hfc_7f;
test004_expected_e_mem[23] = 16'hfe_3f;
test004_expected_e_mem[24] = 16'h0f_ff;
test004_expected_e_mem[25] = 16'h87_ff;
test004_expected_e_mem[26] = 16'hc3_ff;
test004_expected_e_mem[27] = 16'he1_ff;
test004_expected_e_mem[28] = 16'hf0_ff;
test004_expected_e_mem[29] = 16'hf8_7f;
test004_expected_e_mem[30] = 16'hfc_3f;
test004_expected_e_mem[31] = 16'hfe_1f;
test004_expected_e_mem[32] = 16'h07_ff;
test004_expected_e_mem[33] = 16'h83_ff;
test004_expected_e_mem[34] = 16'hc1_ff;
test004_expected_e_mem[35] = 16'he0_ff;
test004_expected_e_mem[36] = 16'hf0_7f;
test004_expected_e_mem[37] = 16'hf8_3f;
test004_expected_e_mem[38] = 16'hfc_1f;
test004_expected_e_mem[39] = 16'hfe_0f;
test004_expected_e_mem[40] = 16'h03_ff;
test004_expected_e_mem[41] = 16'h81_ff;
test004_expected_e_mem[42] = 16'hc0_ff;
test004_expected_e_mem[43] = 16'he0_7f;
test004_expected_e_mem[44] = 16'hf0_3f;
test004_expected_e_mem[45] = 16'hf8_1f;
test004_expected_e_mem[46] = 16'hfc_0f;
test004_expected_e_mem[47] = 16'hfe_07;
test004_expected_e_mem[48] = 16'h01_ff;
test004_expected_e_mem[49] = 16'h80_ff;
test004_expected_e_mem[50] = 16'hc0_7f;
test004_expected_e_mem[51] = 16'he0_3f;
test004_expected_e_mem[52] = 16'hf0_1f;
test004_expected_e_mem[53] = 16'hf8_0f;
test004_expected_e_mem[54] = 16'hfc_07;
test004_expected_e_mem[55] = 16'hfe_03;
end
endtask