`timescale 10ps / 10ps  //1unit = 0.01ns

`define CYCLE_TIME	1600

module top_level();

`include "rcp.vh"

// ri_test inputs

wire reset_l;
wire ri_cbus_read_enable;
wire ri_cbus_write_enable;
wire [CBUS_COMMAND_SIZE-1:0] cbus_command;
wire ri_read_grant;
wire bus_clk;

// ri_test outputs

wire dma_ready;
wire dma_start;
wire dma_last;
wire ri_read_request;
wire sp_dbus_read_enable;
wire mi_dbus_read_enable;
wire span_dbus_read_enable;
wire sp_dbus_write_enable;
wire mi_dbus_write_enable;
wire pi_dbus_write_enable;
wire si_dbus_write_enable;
wire span_dbus_write_enable;
wire [CBUS_DATA_SIZE-1:0] cbus_data;
wire [DBUS_DATA_SIZE-1:0] dbus_data;
wire [EBUS_DATA_SIZE-1:0] ebus_data;
wire clock;
wire c_ctl_ld;

ri_test ri_test_0(reset_l, ri_cbus_read_enable, ri_cbus_write_enable,
	      cbus_command, ri_read_grant, bus_clk,
	      dma_ready, dma_start, dma_last, ri_read_request,
	      sp_dbus_read_enable, mi_dbus_read_enable, span_dbus_read_enable,
	      sp_dbus_write_enable, mi_dbus_write_enable,
	      pi_dbus_write_enable, si_dbus_write_enable,
	      span_dbus_write_enable,
	      cbus_data, dbus_data, ebus_data,
	      clock,
	      c_ctl_ld);

driver driver_0(reset_l, ri_cbus_read_enable, ri_cbus_write_enable,
	      cbus_command, ri_read_grant, bus_clk,
	      dma_ready, dma_start, dma_last, ri_read_request,
	      sp_dbus_read_enable, mi_dbus_read_enable, span_dbus_read_enable,
	      sp_dbus_write_enable, mi_dbus_write_enable,
	      pi_dbus_write_enable, si_dbus_write_enable,
	      span_dbus_write_enable,
	      cbus_data, dbus_data, ebus_data,
	      clock,
	      c_ctl_ld);
endmodule