cop0.c 18.5 KB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697
/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/
/*
#define SP_VERBOSE
*/

/*
 * File:	cop0.c
 * Creator:	hsa@sgi.com
 * Create Date:	Tue Feb  8 11:49:51 PST 1994
 *
 * This file is the simulated coprocessor 0 for the RSP simulator.
 *
 */

#include <stdio.h>
#include "rsp.h"
#include "memory.h"
#include "rspctl.h"
#include "cop0.h"

/* the DMA control registers: */
dma_controlReg_t	dma_controlReg[2];
int			semaphore_old = 0;
int			semaphore_lock = 0;

#define	DMA_CURRENT	0
#define	DMA_PENDING	1

/* the free running counter */
i32	counter_clock;

/* 
 * RDP CMD registers:
 *
 * These are faked here for stand-alone simulation.
 * This module will fake the consumer side by copying
 * things into SCRATCH_MEM.
 *
 */
typedef struct {
    u32		start, end, current;
    u32		status, clock;
    u32		busy, pipe_busy, tmem_busy;
    u32		new_start, new_end;
    boolean	has_new_start, has_new_end;
} rdp_cmd_t;
static rdp_cmd_t	rdp_cmd_regs;

/*
 * fake RDP fifo
 * 
 * The fake RDP fifo copies RDP data to scratch mem (0x20000010),
 * and stores the length of the total RDP data at 0x20000000.
 *
 * It copies data when (current < end), updating current as it goes.
 *
 */
typedef struct {
    u32		ptr;
    u32		count;
} rdp_fifo_t;
static rdp_fifo_t	rdp_fifo;

/*
 * Initialize coprocessor 0 (counters, DMA controller) and the memory
 */
boolean
cop0_Init(char *init_filename, u32 baseaddr)
{
    if (init_filename != (char *) NULL) {
	if (!rsp_MemLoad(init_filename, baseaddr)) {
	    rsp_eprintf(stderr,"cop0_Init : FAILED.\n");
	    return(FALSE);
	}
    }

    counter_clock = 0x0;

    /* fake RDP command registers: */
    bzero((char *) &rdp_cmd_regs, sizeof(rdp_cmd_t));

    /* fake RDP fifo: */
    rdp_fifo.ptr = rsp_SCRATCH_LOW + 0x10;
    rdp_fifo.count = 0;

    rsp_ProcessorStepInstall(cop0_Step);
    return(TRUE);
}

/*
 * Set a coprocessor 0 register (mtc0) and perform associated actions
 */
void
cop0_RegSet(int reg, u32 value)
{
    register dma_controlReg_t	*drp = &dma_controlReg[DMA_CURRENT];
    register rdp_cmd_t		*cmdp = &rdp_cmd_regs;

#if 0
/*
 * This test is bogus; there are many reasonable conditions where
 * you want to set a cop0 register while dma is full...
 * Preventing the bad cases is the programmer's job.
 * Sun Oct 15 18:19:14 PDT 1995
 */
    if (Flagged(rsp_controlReg, dma_FULL)) {
	rsp_eprintf(stderr,"rsp : ERROR : DMA Full! %08x\n", rsp_programCounter);
	rsp_SuSpecialBreak(0x0);
	return;
    }
#endif

    if (Flagged(rsp_controlReg, dma_BUSY))
	drp = &dma_controlReg[DMA_PENDING];
    else
	drp = &dma_controlReg[DMA_CURRENT];

    switch (reg) {

      case 0:
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 0 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	if ((value & 0x07) != 0x00) {
	    rsp_eprintf(stderr,"rsp : cop0.0 DMEM addr bad.\n");
	    rsp_SuSpecialBreak(0x0);
	}
	drp->cacheAddr = value & 0xfffffff8;
	break;

      case 1:
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 1 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	if ((value & 0x07) != 0x00) {
	    rsp_eprintf(stderr,"rsp : cop0.1 DRAM addr bad.\n");
	    rsp_SuSpecialBreak(0x0);
	}
	drp->memAddr = value & 0xfffffff8;
	break;

      case 2:
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 2 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	value |= 0x07;
	if ((value & 0x07) != 0x07) {
	    rsp_eprintf(stderr,"rsp : cop0.2 READ length bad.\n");
	    rsp_SuSpecialBreak(0x0);
	}
	drp->dmaType = dma_READ;
	drp->byteCount = drp->byteCurrent = BYTECOUNT(value) + 1;
	drp->lineCount = LINECOUNT(value) + 1;
	drp->lineStride = LINESTRIDE(value);
	if (Flagged(rsp_controlReg, dma_BUSY))
	    rsp_controlReg = Flag(rsp_controlReg, dma_FULL);
	else
	    rsp_controlReg = Flag(rsp_controlReg, dma_BUSY);
	break;

      case 3:
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 3 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	value |= 0x07;
	if ((value & 0x07) != 0x07) {
	    rsp_eprintf(stderr,"rsp : cop0.3 WRITE length bad.\n");
	    rsp_SuSpecialBreak(0x0);
	}
	drp->dmaType = dma_WRITE;
	drp->byteCount = drp->byteCurrent = BYTECOUNT(value) + 1;
	drp->lineCount = LINECOUNT(value) + 1;
	drp->lineStride = LINESTRIDE(value);
	if (Flagged(rsp_controlReg, dma_BUSY))
	    rsp_controlReg = Flag(rsp_controlReg, dma_FULL);
	else
	    rsp_controlReg = Flag(rsp_controlReg, dma_BUSY);
	break;

      case 4:	/* DMA status */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 4 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
        if (value & SP_CLR_HALT) {                /* clear halt */
            rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_HALT);
        }

        if (value & SP_SET_HALT) {                /* set halt */
            rsp_controlReg = Flag(rsp_controlReg, SP_STATUS_HALT);
        }

        if (value & SP_CLR_BROKE) {               /* clear broke */
            rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_BROKE);
        }

        if (value & SP_CLR_INTR) {                /* clear rsp interrupt */
            /* ? */
        }

        if (value & SP_SET_INTR) {                /* set rsp interrupt */
            /* ? */
        }

        if (value & SP_CLR_SSTEP) {       /* clear single step */
            rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_SSTEP);
        }

        if (value & SP_SET_SSTEP) {       /* set single step */
            rsp_controlReg = Flag(rsp_controlReg, SP_STATUS_SSTEP);
        }

        if (value & SP_CLR_SIG0) {                /* clear signal 0 */
            rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_SIG0);
        }

        if (value & SP_SET_SIG0) {                /* set signal 0 */
            rsp_controlReg = Flag(rsp_controlReg, SP_STATUS_SIG0);
        }

        if (value & SP_CLR_SIG1) {                /* clear signal 1 */
            rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_SIG1);
        }

        if (value & SP_SET_SIG1) {                /* set signal 1 */
            rsp_controlReg = Flag(rsp_controlReg, SP_STATUS_SIG1);
        }

        if (value & SP_CLR_SIG2) {                /* clear signal 2 */
            rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_SIG2);
        }

        if (value & SP_SET_SIG2) {                /* set signal 2 */
            rsp_controlReg = Flag(rsp_controlReg, SP_STATUS_SIG2);
        }

        if (value & SP_CLR_SIG3) {                /* clear signal 3 */
            rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_SIG3);
        }

        if (value & SP_SET_SIG3) {                /* set signal 3 */
            rsp_controlReg = Flag(rsp_controlReg, SP_STATUS_SIG3);
        }

        if (value & SP_CLR_INTR_BREAK) {  /* clear interrupt on break */
            /* ? */

        }

        if (value & SP_SET_INTR_BREAK) {  /* set interrupt on break */
            /* ? */
        }
	break;

      case 5:	/* DMA full */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 5 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	/* can't set, READ ONLY */
	break;

      case 6:	/* DMA busy */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 6 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	/* can't set, READ ONLY */
	break;

      case 7:	/* semaphore */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 7 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	semaphore_lock = 0;
	break;

      case 8:	/* CMD START */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 8 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	if ((value & 0x07) != 0x00) {
	    rsp_eprintf(stderr,"rsp : cop0.8 CMD START addr bad.\n");
	    rsp_SuSpecialBreak(0x0);
	}
	if (!cmdp->busy) {	/* copy directly to registers */
	    cmdp->start   = value & 0xfffffff8;
	    cmdp->current = value & 0xfffffff8;
	    cmdp->end     = value & 0xfffffff8;
	} else {		/* double-buffer */
	    cmdp->new_start = value & 0xfffffff8;
	    cmdp->has_new_start = TRUE;
	}
	break;

      case 9:	/* CMD END */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 9 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	if ((value & 0x07) != 0x00) {
	    rsp_eprintf(stderr,"rsp : cop0.9 CMD END addr bad.\n");
	    rsp_SuSpecialBreak(0x0);
	}
/*	if (!cmdp->busy) {	/* copy directly to registers */
	if (!cmdp->has_new_start) {	/* copy directly to registers */
	    cmdp->end = value & 0xfffffff8;
	} else {		/* double-buffer */
	    cmdp->new_end = value & 0xfffffff8;
	    cmdp->has_new_end = TRUE;
	}
	break;

      case 10:	/* CMD CURRENT */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 10 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	/* can't set, READ ONLY */
	break;

      case 11:	/* CMD STATUS */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 11 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	break;

      case 12:	/* CMD CLOCK */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 12 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	counter_clock = (i32)value;
	break;

      case 13:	/* CMD BUSY */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 13 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	/* can't set, READ ONLY */
	break;

      case 14:	/* CMD PIPE BUSY */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 14 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	/* can't set, READ ONLY */
	break;

      case 15:	/* CMD TMEM BUSY */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> write io reg 15 [0x%08X]\n",(int) value);
#endif /* SP_VERBOSE */
	/* can't set, READ ONLY */
	break;

      default:
	break;
    }
}

u32
cop0_RegGet(int reg)
{
    register dma_controlReg_t	*drp = &dma_controlReg[DMA_CURRENT];
    register rdp_cmd_t		*cmdp = &rdp_cmd_regs;

    switch (reg) {

      case 0:	/* dma cache address */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 0 as [0x%08X]\n",(int) drp->cacheAddr);
#endif /* SP_VERBOSE */
	return(drp->cacheAddr);
	break;

      case 1:	/* dma DRAM address */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 1 as [0x%08X]\n",(int) drp->memAddr);
#endif /* SP_VERBOSE */
	return(drp->memAddr);
	break;

      case 2:	/* dma read length */
	if (drp->dmaType == dma_READ && Flagged(rsp_controlReg, dma_BUSY)) {
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 2 as [0x%08X]\n",(int) LENGTHREG(drp->lineStride, drp->lineCount - 1,drp->byteCurrent - 1));
#endif /* SP_VERBOSE */
	    return(LENGTHREG(drp->lineStride, drp->lineCount - 1,
			     drp->byteCurrent - 1));
	} else {
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 2 as [0x%08X]\n",(int) -1);
#endif /* SP_VERBOSE */
	    return (u32) -1;
	}
	break;

      case 3:	/* dma write length */
	if (drp->dmaType == dma_WRITE && Flagged(rsp_controlReg, dma_BUSY)) {
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 3 as [0x%08X]\n",(int) LENGTHREG(drp->lineStride, drp->lineCount - 1,drp->byteCurrent - 1));
#endif /* SP_VERBOSE */
	    return(LENGTHREG(drp->lineStride, drp->lineCount - 1,
			     drp->byteCurrent - 1));
	} else {
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 3 as [0x%08X]\n",(int) -1);
#endif /* SP_VERBOSE */
	    return (u32) -1;
	}
	break;

      case 4:	/* dma status */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 4 as [0x%08X]\n",(int) rsp_controlReg);
#endif /* SP_VERBOSE */
	return rsp_controlReg;
	break;

      case 5:	/* dma full */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 5 as [0x%08X]\n",(int) Flagged(rsp_controlReg, dma_FULL));
#endif /* SP_VERBOSE */
	return Flagged(rsp_controlReg, dma_FULL);
	break;

      case 6:	/* dma busy */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 6 as [0x%08X]\n",(int) Flagged(rsp_controlReg, dma_BUSY));
#endif /* SP_VERBOSE */
	return Flagged(rsp_controlReg, dma_BUSY);
	break;

      case 7:	/* semaphore */
	semaphore_old = semaphore_lock;
	semaphore_lock = 1;
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 7 as [0x%08X]\n",(int) semaphore_old);
#endif /* SP_VERBOSE */
	return semaphore_old;
	break;

      case 8:	/* CMD START */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 8 as [0x%08X]\n",(int) cmdp->start);
#endif /* SP_VERBOSE */
	return (cmdp->start);
	break;

      case 9:	/* CMD END */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 9 as [0x%08X]\n",(int) cmdp->end);
#endif /* SP_VERBOSE */
	return (cmdp->end);
	break;

      case 10:	/* CMD CURRENT */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 10 as [0x%08X]\n",(int) cmdp->current);
#endif /* SP_VERBOSE */
	return (cmdp->current);
	break;

      case 11:	/* CMD STATUS */
	cmdp->status &= ~0x600;
	cmdp->status |= (cmdp->has_new_start) ? 0x400 : 0;
	cmdp->status |= (cmdp->has_new_end) ? 0x200 : 0;
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 11 as [0x%08X]\n",(int) cmdp->status);
#endif /* SP_VERBOSE */
	return (cmdp->status);
	break;

      case 12:	/* CMD CLOCK */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 12 as [0x%08X]\n",(int) counter_clock);
#endif /* SP_VERBOSE */
	return (u32) counter_clock;
	break;

      case 13:	/* CMD BUSY */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 13 as [0x%08X]\n",(int) cmdp->busy);
#endif /* SP_VERBOSE */
	return (cmdp->busy);
	break;

      case 14:	/* CMD PIPE BUSY */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 14 as [0x%08X]\n",(int) cmdp->pipe_busy);
#endif /* SP_VERBOSE */
	return (cmdp->pipe_busy);
	break;

      case 15:	/* CMD TMEM BUSY */
#ifdef SP_VERBOSE
fprintf(stderr,"RSPSIM--> READ io reg 15 as [0x%08X]\n",(int) cmdp->tmem_busy);
#endif /* SP_VERBOSE */
	return (cmdp->tmem_busy);
	break;

      default:
	break;
    }
}

boolean
cop0_DmaBusy(void)
{
    return (Flagged(rsp_controlReg, dma_BUSY) ? TRUE : FALSE);
}

boolean
cop0_DmaFull(void)
{
    return (Flagged(rsp_controlReg, dma_FULL) ? TRUE : FALSE);
}

/*
 * Does one clock-tick of activity of coprocessor 0.
 * Only allowed to be called from the simulator control unit.
 *
 * Can transfer up to 64-bits per clock tick.
 */

/* DMAWAIT delays writing to simulate a slow RDP.  The bigger the number,
 * the slower the RDP.  Use -1 for fastest RDP
 */
/*#define DMAWAIT 100*/
#define DMAWAIT -1
static int dmawait=DMAWAIT;

boolean
cop0_TestXBUS(void)
{
    register rdp_cmd_t		*cmdp = &rdp_cmd_regs;

    if (cmdp->current < cmdp->end) {
	return(TRUE);
    } else {
	return(FALSE);
    }
}

boolean
cop0_Step(void)
{
    register dma_controlReg_t	*drp = &dma_controlReg[DMA_CURRENT];
    register rdp_cmd_t		*cmdp = &rdp_cmd_regs;
    register rdp_fifo_t		*fifop = &rdp_fifo;
    u8				byte;
    int				i;

    /* increment the free running counter */
    counter_clock++;

    /* 
     * do the fake RDP fifo:
     * If current < end, copy data and set flags accordingly.
     */
    if (cmdp->current < cmdp->end) {
      if (dmawait--<=0) {
        dmawait = DMAWAIT;

#ifdef SP_VERBOSE
	printf("DOING start=0x%08X end=0x%08X current=0x%08X TO=0x%08X WORD=0x"
			,cmdp->start,cmdp->end,cmdp->current,fifop->ptr);
#endif /* SP_VERBOSE */

	for (i=0; i<8 && (cmdp->current < cmdp->end); i++) {

	    if (XBUS_stdout) {
		    byte = rsp_MemReadByte(cmdp->current, rsp_DCACHE_ACCESS);
		    fwrite(&byte, sizeof(u8), 1, stdout);
#ifdef SP_VERBOSE
		    printf("%02X",(int) byte);
#endif /* SP_VERBOSE */
		    cmdp->current++;
		    fifop->ptr++;
		    fifop->count++;
	    } else {
		    byte = rsp_MemReadByte(cmdp->current, rsp_DCACHE_ACCESS);
		    rsp_MemWriteByte(fifop->ptr, byte, rsp_ABSOLUTE_ACCESS);
#ifdef SP_VERBOSE
		    printf("%02X",(int) byte);
#endif /* SP_VERBOSE */
		    cmdp->current++;
		    fifop->ptr++;
		    fifop->count++;
		    rsp_MemWriteWord(rsp_SCRATCH_LOW, fifop->count, 
				 rsp_ABSOLUTE_ACCESS);
	    }
	}
#ifdef SP_VERBOSE
printf("\n");
#endif /* SP_VERBOSE */
	/* any more to transfer? */
	if (cmdp->current >= cmdp->end)
	    cmdp->busy = FALSE;
	else
	    cmdp->busy = TRUE;
      }
    }

    /* if we transitioned from BUSY to NOT BUSY, check to see
     * if we have any pending requests. If so, copy them to
     * the registers.
     */
    if (!cmdp->busy) {
	if (cmdp->has_new_start) {
	    cmdp->start = cmdp->new_start;
	    cmdp->current = cmdp->new_start;
	    cmdp->has_new_start = FALSE;
	}

	if (cmdp->has_new_end) {
	    cmdp->end = cmdp->new_end;
	    cmdp->has_new_end = FALSE;
	}

    }

    if (!Flagged(rsp_controlReg, dma_BUSY)) {
	return FALSE;	/* not doing anything... */
    }

    /* transfer (up to) one 64-bit word per clock tick: */

    switch (drp->dmaType) {
      case dma_READ:
#ifdef SP_VERBOSE
	fprintf(stderr,"~~~~DMA READ  0x");
#endif /* SP_VERBOSE */
	for (i=0; i<8 && drp->byteCurrent > 0; i++, drp->byteCurrent--) {
	    byte = rsp_MemReadByte(drp->memAddr,rsp_ABSOLUTE_ACCESS);
#ifdef SP_VERBOSE
	fprintf(stderr,"%02X",byte);
#endif /* SP_VERBOSE */
	    if (drp->cacheAddr & 0x1000)
		rsp_MemWriteByte(drp->cacheAddr,byte,rsp_ICACHE_ACCESS);
	    else
		rsp_MemWriteByte(drp->cacheAddr,byte,rsp_DCACHE_ACCESS);
	    drp->cacheAddr++;
	    drp->memAddr++;
	}
#ifdef SP_VERBOSE
	fprintf(stderr,"\n");
#endif /* SP_VERBOSE */
	break;

      case dma_WRITE:
#ifdef SP_VERBOSE
	fprintf(stderr,"~~~~DMA WRITE 0x");
#endif /* SP_VERBOSE */
	for (i=0; i<8 && drp->byteCurrent > 0; i++, drp->byteCurrent--) {
	    byte = rsp_MemReadByte(drp->cacheAddr,rsp_DCACHE_ACCESS);
#ifdef SP_VERBOSE
	    fprintf(stderr,"%02X",byte);
#endif /* SP_VERBOSE */
	    rsp_MemWriteByte(drp->memAddr, byte,rsp_ABSOLUTE_ACCESS);
	    drp->cacheAddr++;
	    drp->memAddr++;
	}
#ifdef SP_VERBOSE
	fprintf(stderr,"\n");
#endif /* SP_VERBOSE */
	break;

    }

    if (drp->byteCurrent == 0) {
	drp->byteCurrent = drp->byteCount;
	drp->lineCount--;
/*	drp->cacheAddr += drp->lineStride; */
	drp->memAddr += drp->lineStride;
    }
    if (drp->lineCount == 0) {
	rsp_Verbose(stderr,"DMA finished.\n");
	/*
	 * copy no matter what, just in case we're in the middle of
	 * setting up the next DMA when BUSY goes away.  -- eyw
	 */
	dma_controlReg[DMA_CURRENT] = dma_controlReg[DMA_PENDING];
	if (Flagged(rsp_controlReg, dma_FULL)) {
	    rsp_controlReg = UnFlag(rsp_controlReg, dma_FULL);
	} else {
	    rsp_controlReg = UnFlag(rsp_controlReg, dma_BUSY);
	}
    }

    return TRUE;
}