/**************************************************************************
 *                                                                        *
 *               Copyright (C) 1994, Silicon Graphics, Inc.               *
 *                                                                        *
 *  These coded instructions, statements, and computer programs  contain  *
 *  unpublished  proprietary  information of Silicon Graphics, Inc., and  *
 *  are protected by Federal copyright  law.  They  may not be disclosed  *
 *  to  third  parties  or copied or duplicated in any form, in whole or  *
 *  in part, without the prior written consent of Silicon Graphics, Inc.  *
 *                                                                        *
 *************************************************************************/

/*
 * File:	memory.c
 * Creator:	hsa@sgi.com
 * Create Date:	Mon Feb 14 13:04:36 PST 1994
 *
 * This is the low-level memory module for the RSP simulator.
 * Only two modules talk to this directly: the DMA engine (of course),
 * and the simulator debugger.
 *
 */

/*
 * Memory Layout:
 *
 * The RSP is a memory-mapped architecture; the layout here is
 * a simple (arbitrary) choice just to get started.
 *
 *    0x00000000   - --------------------
 *                   |                  |
 *                   |                  |
 *                   |      2MB         |
 *                   |      DRAM        |
 *                   |                  |
 *                   |                  |
 *                   |                  |
 *    0x00200000    -|------------------|
 *                   .                  .  DRAM has 26-bit addressing
 *                   .                  .
 *                   .                  .
 *                   .  could be 64MB   .
 *                   .  of DRAM         .
 *                   .                  .
 *                   .                  .
 *    0x03ffffff    -|                  |
 *    0x04000000    -|------------------|
 *                   |                  |
 *                   | 4K of RSP DMem   |
 *                   |                  |
 *    0x04001000    -|------------------|
 *                   |                  |
 *                   | 4K of RSP IMem   |
 *                   | (1K instructions)|
 *                   |                  |
 *                   |------------------|
 *                   .                  .
 *                   .                  .
 *                   .                  .
 *    0x10003000    -|------------------|
 *                   |                  |
 *                   | RSP registers    |
 *                   | memory-mapped    |
 *                   |                  |
 *                   .                  .
 *                   .                  .
 *                   .                  .
 *    0x10010000    -|------------------|
 *                   | Trig ROM         |
 *                   |                  |
 *    0x....        -|------------------|
 *                   .                  .
 *                   . other I/O        .
 *                   . (audio, video,   .
 *                   . RDP, ...         .
 *                   .                  .
 *                   .                  .
 *
 */

#include <stdio.h>
#include <math.h>	/* for trig stub */
#include <errno.h>
#include <rcp.h>
#include "rsp.h"
#include "rspctl.h"
#include "memory.h"

/* This is the main memory: */
u8 	rsp_mainMemory_p[rsp_DRAM_SIZE8];

/* the data cache: */
u8 	rsp_dataCache_p[rsp_DCACHE_SIZE8];

/* The instruction cache: */
u8	rsp_instructionCache_p[rsp_ICACHE_SIZE8];

/* This is the scratch memory: (see comment in memory.h) */
u8 	rsp_scratchMemory_p[rsp_SCRATCH_SIZE8];

/*
 * the global pointers are separate from the actual memory, so
 * we can redirect the memory (like to shared memory)
 */
u8 	*rsp_mainMemory;
u8 	*rsp_dataCache;
u8	*rsp_instructionCache;
u8 	*rsp_scratchMemory;

/* The Trig ROM: */
#include "sintable.h"
u32	rsp_trigROM[2];		/* see comment below... */
static void	rsp_fillTrig(u32 addr);

/*
 * Macros for addressing memory. They are here, not in memory.h, because
 * nobody else should be calling them.
 */
#define mem_AddrIsDRAM(addr)	((u32)(addr) >= rsp_DRAM_LOW &&		\
				 (u32)(addr) < rsp_DRAM_LOW + rsp_DRAM_SIZE8)
#define mem_AddrIsDCACHE(addr)	((u32)(addr) >= rsp_DCACHE_LOW && 	\
				 (u32)(addr) < rsp_DCACHE_LOW + rsp_DCACHE_SIZE8)
#define mem_AddrIsICACHE(addr)	((u32)(addr) >= rsp_ICACHE_LOW && 	\
				 (u32)(addr) < rsp_ICACHE_LOW + rsp_ICACHE_SIZE8)
#define mem_AddrIsGPR(addr)	((u32)(addr) >= rsp_GPR_LOW &&		\
				 (u32)(addr) < rsp_GPR_LOW + rsp_GPR_SIZE8)
#define mem_AddrIsDMA(addr)	((u32)(addr) >= rsp_DMA_LOW &&		\
				 (u32)(addr) < rsp_DMA_LOW + rsp_DMA_SIZE8)
#define mem_AddrIsTrig(addr)	(((u32)(addr) & 0xffff0000) == 0x10010000)

#define mem_AddrIsSCRATCH(addr)	((u32)(addr) >= rsp_SCRATCH_LOW &&		\
				 (u32)(addr) < rsp_SCRATCH_LOW + rsp_SCRATCH_SIZE8)

extern void	rsp_CheckWatchpoint(u32 addr);

void
rsp_MemoryInit(void)
{
    rsp_mainMemory = rsp_mainMemory_p;
    rsp_dataCache = rsp_dataCache_p;
    rsp_instructionCache = rsp_instructionCache_p;
    rsp_scratchMemory = rsp_scratchMemory_p;
}

/*
 * Trig ROM:
 *
 * In order to fit in with the other memory routines, it does the
 * table lookup, then puts the answer in a temporary storage to be read...
 *
 * addr is from 0-4095, the sin/cos values of the unit circle.
 *
 */
static void
rsp_fillTrig(u32 addr)
{
    i16		x, val;

    /* compute sin: */
#define sine(x)					\
    if (x & 0x400) {				\
	val = sintable[0x3ff - (x & 0x3ff)];	\
    } else {					\
	val = sintable[x & 0x3ff];		\
    }						\
    if (x & 0x800) {				\
	val = -val;				\
    }

    x = addr;
    sine(x);
    rsp_trigROM[0] = val;
    rsp_trigROM[0] <<= 16;

    /* compute cos: */
    x = addr + 0x400;
    x &= 0x00000fff;
    sine(x);
    rsp_trigROM[0] |= (0x0000ffff & (i32)val);
}

/********************** standalone debugging support ***********************/
/*
 * The following are simulator-only routines, designed to allow
 * the user to peek/poke the memory while the processor is
 * halted.
 */

/*
 * utility routine that accepts an address and an address of a base pointer.
 * returns the 'normalized' address and the base pointer filled
 * in. (sets baseptr to be bottom of {DRAM | DMem | IMem} and adjusts addr)
 */
static u32
translate_addr(u32 addr, u8 **baseptr)
{
    u8		*memptr = (u8 *) NULL;
    extern int rsp_disable_scratch_mem;

    rsp_CheckWatchpoint(addr);

    /* should prevent boundary crossing... */

    if (mem_AddrIsDRAM(addr)) {
	memptr = &(rsp_mainMemory[0]);
	addr -= rsp_DRAM_LOW;
    } else if (mem_AddrIsDCACHE(addr)) {
	memptr = &(rsp_dataCache[0]);
	addr -= rsp_DCACHE_LOW;
    } else if (mem_AddrIsICACHE(addr)) {
	memptr = &(rsp_instructionCache[0]);
	addr -= rsp_ICACHE_LOW;
    } else if (mem_AddrIsGPR(addr)) {
	/*
	 * since this is the RSP simulator, and it's the
	 * host CPU and RDP that might want to do this, I
	 * haven't implemented this yet...
	 */
    } else if (mem_AddrIsDMA(addr)) {
	/*
	 * nobody will do it this way...
	 */
    } else if (mem_AddrIsTrig(addr)) {
	rsp_fillTrig(addr & 0x00000fff);
	memptr = (char *) &(rsp_trigROM[0]);
	addr = 0;
    } else if (mem_AddrIsSCRATCH(addr)) {

	if ( rsp_disable_scratch_mem ) {
	    rsp_eprintf(stderr,"ERROR : Scratch Memory disabled (addr = %08x)\n",addr);
	    rsp_SuSpecialBreak(0x0);
	} else {
	    memptr = &(rsp_scratchMemory[0]);
	    addr -= rsp_SCRATCH_LOW;
	};

    } else {
	rsp_eprintf(stderr,"ERROR : invalid address: %08x\n",addr);
	rsp_SuSpecialBreak(0x0);
    }

    *baseptr = memptr;

    return addr;
}

/*
 * utility routine that accepts an address and the type of memory it should be 
 * in.  memtype = the type of memory: rsp_DCACHE_ACCESS (DCACHE memory) or
 * rsp_ICACHE_ACCESS (ICACHE memory) or rsp_ABSOLUTE_ACCESS (any other memory).
 * The rsp ignores all but the significant bits in the DCACHE and ICACHE
 * memory ranges, so accesses supposedly aimed at those ranges will always go
 * to that range even if the high bits point somewhere else.  This routine
 * strips off the high bits and ensures that the access goes to the correct
 * memory block.  Scratch memory addresses (0x20000000-0x201fffff, which is
 * used on the simulator but will not exist in the hardware) are not altered
 * so they will still access the protected range.
 */
static u32
alias_addr(u32 addr, int memtype)
{
	u32 retaddr;
	extern int rsp_disable_scratch_mem;

	retaddr = addr;
	if ( rsp_disable_scratch_mem ||
	     (addr < rsp_SCRATCH_LOW) || (addr >= rsp_SCRATCH_LOW+rsp_SCRATCH_SIZE8))
		switch (memtype) {
			case rsp_DCACHE_ACCESS :
				retaddr = (addr & rsp_DCACHE_BITS) + rsp_DCACHE_LOW;
				break;
			case rsp_ICACHE_ACCESS :
				retaddr = (addr & rsp_ICACHE_BITS) + rsp_ICACHE_LOW;
				break;
			default:
				break;
		}
	return retaddr;
}

/*
 * initialize DRAM from a file:
 */
boolean
rsp_MemLoad(char *filename, u32 baseaddr)
{
    FILE	*init_file;
    u32		addr;
    u8		*baseptr;
    int		byte;

    if ((init_file = fopen(filename, "r")) == NULL) {
	rsp_eprintf(stderr,"ERROR : could not load memory from [%s]. %d\n",
		filename, errno);
	return(FALSE);
    }

    addr = translate_addr(baseaddr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not load memory from [%s]. (base NULL)\n",
		filename);
	fclose(init_file);
	return(FALSE);
    }

    /* the format of this file should probably handle offsets, etc. */
    while ((byte = fgetc(init_file)) != EOF && !ferror(init_file)) {
	baseptr[addr++] = byte;
    }

    fclose(init_file);
    return(TRUE);
}

/*
 * write DRAM to a file:
 */
boolean
rsp_MemUnLoad(char *filename, u32 baseaddr, u32 length, boolean doAppend)
{
    FILE	*output_file;
    u32		i, addr;
    u8		*baseptr;
    int		byte;
    char	*modeFlag[2] = {"w", "a"};

    if ((output_file = fopen(filename, modeFlag[doAppend])) == NULL) {
	rsp_eprintf(stderr,"ERROR : could not save main memory to [%s].\n",
		filename);
	return(FALSE);
    }

    addr = translate_addr(baseaddr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not save main memory to [%s].\n",
		filename);
	fclose(output_file);
	return(FALSE);
    }

    for (i=0; i<length; i++) {
	fputc(baseptr[addr++], output_file);
    }

    fclose(output_file);
    return(TRUE);
}

/*
 * do a bcopy between memory pieces.
 */
boolean
rsp_MemBcopy(u32 from, u32 to, u32 length)
{
    u32		*word;
    u8		*fromptr, *toptr, *frombase, *tobase;

    from = translate_addr(from, &frombase);
    to = translate_addr(to, &tobase);

    if (frombase == (u8 *) NULL || tobase == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not do bcopy.\n");
	return(FALSE);
    }

    fromptr = &(frombase[from]);
    toptr = &(tobase[from]);

    bcopy(fromptr, toptr, length);

    return(TRUE);
}

/*
 * do a bcopy between memory and IPC buffer.
 */
boolean
rsp_MemToIPC(u32 from, u32 to, u32 length)
{
    u8		*fromptr, *frombase;

    from = translate_addr(from, &frombase);

    if (frombase == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not do bcopy.\n");
	return(FALSE);
    }

    fromptr = &(frombase[from]);

    bcopy(fromptr, (char *)to, length);

    return(TRUE);
}

/*
 * do a bcopy between memory and IPC buffer.
 */
boolean
rsp_MemFromIPC(u32 from, u32 to, u32 length)
{
    u8		*toptr, *tobase;

    to = translate_addr(to, &tobase);

    if (tobase == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not do bcopy.\n");
	return(FALSE);
    }

    toptr = &(tobase[to]);

    bcopy((char *)from, toptr, length);

    return(TRUE);
}

/*
 * byte read
 */
u8
rsp_MemReadByte(u32 addr,int memtype)
{
    u8		*baseptr;

	addr = alias_addr(addr,memtype);

    addr = translate_addr(addr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not access memory.\n");
	return(0);
    }

    return(baseptr[addr]);
}

/*
 * halfword read
 */
u16
rsp_MemReadHalf(u32 addr,int memtype)
{
    u8		*baseptr;
    u16		tmp;

	addr = alias_addr(addr,memtype);

    addr = translate_addr(addr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not access memory.\n");
	return(0);
    }

    if (baseptr == &(rsp_scratchMemory[0])) {
	tmp = ((u16) baseptr[addr] << 8) | baseptr[(addr+1)];
    } else {
	tmp = ((u16) baseptr[addr] << 8) | baseptr[(addr+1)&0xfff];
    }
    return(tmp);
}

/*
 * word read
 */
u32
rsp_MemReadWord(u32 addr,int memtype)
{
    u8		*baseptr;
    u32		tmp;

	addr = alias_addr(addr,memtype);

    addr = translate_addr(addr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not access memory.\n");
	return(0);
    }

    if (baseptr == &(rsp_scratchMemory[0])) {
	tmp = (((u32) baseptr[(addr+0)] << 24) |
	       ((u32) baseptr[(addr+1)] << 16) |
	       ((u32) baseptr[(addr+2)] <<  8) |
	       ((u32) baseptr[(addr+3)]));
    } else {
	tmp = (((u32) baseptr[(addr+0)&0xfff] << 24) |
	       ((u32) baseptr[(addr+1)&0xfff] << 16) |
	       ((u32) baseptr[(addr+2)&0xfff] <<  8) |
	       ((u32) baseptr[(addr+3)&0xfff]));
    }
    return(tmp);
}

/*
 * double word read
 */
u64
rsp_MemReadDouble(u32 addr,int memtype)
{
    int		i;
    u8		*baseptr;
    u64		tmp;

	addr = alias_addr(addr,memtype);

    addr = translate_addr(addr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not access memory.\n");
	return(0);
    }

    tmp = 0x0000000000000000;
    for (i=0; i<8; i++) {
	if (baseptr == &(rsp_scratchMemory[0])) {
	    tmp |= (((u64)baseptr[(addr + i)]) << ((7-i)*8));
	} else {
	    tmp |= (((u64)baseptr[(addr + i)&0xfff]) << ((7-i)*8));
	}
    }

    return(tmp);
}

/*
 * byte write
 */
void
rsp_MemWriteByte(u32 addr, u8 byte,int memtype)
{
    u8		*baseptr;

	addr = alias_addr(addr,memtype);

    addr = translate_addr(addr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not access memory.\n");
	return;
    }

    baseptr[addr] = byte;
}

/*
 * halfword write
 */
void
rsp_MemWriteHalf(u32 addr, u16 half,int memtype)
{
    u8		*baseptr;

	addr = alias_addr(addr,memtype);

    addr = translate_addr(addr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not access memory.\n");
	return;
    }

    if (baseptr == &(rsp_scratchMemory[0])) {
	baseptr[addr] = (half & 0xff00) >> 8;
	baseptr[(addr+1)] = (half & 0x00ff);
    } else {
	baseptr[addr] = (half & 0xff00) >> 8;
	baseptr[(addr+1)&0xfff] = (half & 0x00ff);
    }
}

/*
 * word write
 */
void
rsp_MemWriteWord(u32 addr, u32 word,int memtype)
{
    u8		*baseptr;

	addr = alias_addr(addr,memtype);

    addr = translate_addr(addr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not access memory.\n");
	return;
    }

    if (baseptr == &(rsp_scratchMemory[0])) {
	baseptr[(addr+0)] = (word & 0xff000000) >> 24;
	baseptr[(addr+1)] = (word & 0x00ff0000) >> 16;
	baseptr[(addr+2)] = (word & 0x0000ff00) >>  8;
	baseptr[(addr+3)] = (word & 0x000000ff);
    } else {
	baseptr[(addr+0)&0xfff] = (word & 0xff000000) >> 24;
	baseptr[(addr+1)&0xfff] = (word & 0x00ff0000) >> 16;
	baseptr[(addr+2)&0xfff] = (word & 0x0000ff00) >>  8;
	baseptr[(addr+3)&0xfff] = (word & 0x000000ff);
    }
}

/*
 * double word write
 */
void
rsp_MemWriteDouble(u32 addr, u64 word,int memtype)
{
    int		i;
    u8		*baseptr;
    u64		mask, tmp;

	addr = alias_addr(addr,memtype);

    addr = translate_addr(addr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not access memory.\n");
	return;
    }

    /* the compiler didn't like shifting the other way... */
    mask = 0x00000000000000ff;
    for (i=7; i>=0; i--) {
	tmp = word & mask;
	tmp >>= (7-i)*8;
	if (baseptr == &(rsp_scratchMemory[0])) {
	    baseptr[(addr + i)] = (u8) tmp;
	} else {
	    baseptr[(addr + i)&0xfff] = (u8) tmp;
	}
	mask <<= 8;
    }
}

/*
 * word-aligned read from debugger:
 */
/* Same as rsp_ExamineMemory, except it uses memtype as the memory base
 * This allows the vertual PC (e.g.  pc starting at address 0).
 * (Kishor 9/26/94)*/

u32
rsp_ExamineMemory1(u32 addr, int memtype)
{
    u32		*word;
    u8		*baseptr;

    addr &= 0xfffffffc;	/* you can only address by word from debugger... */
    
    addr = alias_addr(addr,memtype);
    addr = translate_addr(addr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not access memory.\n");
	return(FALSE);
    }

    word = (u32 *) &(baseptr[addr]);


    return ntohl(*word);
}

/*
 * word-aligned read from debugger:
 */
u32
rsp_ExamineMemory(u32 addr)
{
    u32		*word;
    u8		*baseptr;

    addr &= 0xfffffffc;	/* you can only address by word from debugger... */
    
    addr = translate_addr(addr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not access memory.\n");
	return(FALSE);
    }

    word = (u32 *) &(baseptr[addr]);


    return ntohl(*word);
}

/*
 * word-aligned write from debugger:
 */
u32
rsp_DepositMemory(u32 addr, u32 value)
{
    u32		*word;
    u8		*baseptr;

    addr &= 0xfffffffc;	/* you can only address by word from debugger... */

    addr = translate_addr(addr, &baseptr);

    if (baseptr == (u8 *) NULL) {
	rsp_eprintf(stderr,"ERROR : could not access memory.\n");
	return(FALSE);
    }

    word = (u32 *) &(baseptr[addr]);
    *word = htonl(value);

    return TRUE;
}


/*
 * These next routines read/write a single word using the
 * global RCP memory map. They are called from the IPC
 * module, which is handling requests on behalf of the host CPU.
 *
 */
void
rsp_MemWriteMap(u32 addr, u32 val)
{
    if (addr >= SP_DMEM_START && addr <= SP_DMEM_END) {		/* DMEM */
	rsp_MemWriteWord(addr, val, rsp_DCACHE_ACCESS);
    } else if (addr >= SP_IMEM_START && addr <= SP_IMEM_END) {	/* IMEM */
	rsp_MemWriteWord(addr, val, rsp_ICACHE_ACCESS);
    } else if (addr == SP_MEM_ADDR_REG) {	/* DMA dram address */
	cop0_RegSet(1, val);
    } else if (addr == SP_MEM_ADDR_REG) {	/* DMA sp mem address */
	cop0_RegSet(0, val);
    } else if (addr == SP_RD_LEN_REG) {		/* DMA read length */
	cop0_RegSet(2, val);
    } else if (addr == SP_WR_LEN_REG) {		/* DMA write length */
	cop0_RegSet(3, val);
    } else if (addr == SP_STATUS_REG) {		/* SP status (write) */
	/* further decode necessary: */

	if (val & SP_CLR_HALT) {		/* clear halt */
	    rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_HALT);
	} 

	if (val & SP_SET_HALT) {		/* set halt */
	    rsp_controlReg = Flag(rsp_controlReg, SP_STATUS_HALT);
	}
	
	if (val & SP_CLR_BROKE) {		/* clear broke */
	    rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_BROKE);
	} 

	if (val & SP_CLR_INTR) {		/* clear rsp interrupt */
	    /* ? */
	} 

	if (val & SP_SET_INTR) {		/* set rsp interrupt */
	    /* ? */
	}

	if (val & SP_CLR_SSTEP) {	/* clear single step */
	    rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_SSTEP);
	}

	if (val & SP_SET_SSTEP) {	/* set single step */
	    rsp_controlReg = Flag(rsp_controlReg, SP_STATUS_SSTEP);
	}

	if (val & SP_CLR_SIG0) {		/* clear signal 0 */
	    rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_SIG0);
	}

	if (val & SP_SET_SIG0) {		/* set signal 0 */
	    rsp_controlReg = Flag(rsp_controlReg, SP_STATUS_SIG0);
	}

	if (val & SP_CLR_SIG1) {		/* clear signal 1 */
	    rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_SIG1);
	}

	if (val & SP_SET_SIG1) {		/* set signal 1 */
	    rsp_controlReg = Flag(rsp_controlReg, SP_STATUS_SIG1);
	}

	if (val & SP_CLR_SIG2) {		/* clear signal 2 */
	    rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_SIG2);
	}

	if (val & SP_SET_SIG2) {		/* set signal 2 */
	    rsp_controlReg = Flag(rsp_controlReg, SP_STATUS_SIG2);
	}

	if (val & SP_CLR_SIG3) {		/* clear signal 3 */
	    rsp_controlReg = UnFlag(rsp_controlReg, SP_STATUS_SIG3);
	}

	if (val & SP_SET_SIG3) {		/* set signal 3 */
	    rsp_controlReg = Flag(rsp_controlReg, SP_STATUS_SIG3);
	}

	if (val & SP_CLR_INTR_BREAK) {	/* clear interrupt on break */
	    /* ? */

	}

	if (val & SP_SET_INTR_BREAK) {	/* set interrupt on break */
	    /* ? */
	}

    } else if (addr == SP_DMA_FULL_REG) {	/* SP DMA full */
	/* can't write */
    } else if (addr == SP_DMA_BUSY_REG) {	/* SP DMA busy */
	/* can't write */
    } else if (addr == SP_SEMAPHORE_REG) {	/* SP semaphore (write) */
	cop0_RegSet(7, val);

    } else if (addr == SP_PC_REG) {	/* SP pc */
	rsp_programCounter = (val | 0x04001000);
    } else if (addr == SP_IBIST_REG) {	/* SP IMEM BIST status */
    }
}

u32
rsp_MemReadMap(u32 addr)
{
    u32		word;

    if (addr >= SP_DMEM_START && addr <= SP_DMEM_END) {		/* DMEM */
	word = rsp_MemReadWord(addr, rsp_DCACHE_ACCESS);
    } else if (addr >= SP_IMEM_START && addr <= SP_IMEM_END) {	/* IMEM */
	word = rsp_MemReadWord(addr, rsp_ICACHE_ACCESS);
    } else if (addr == SP_MEM_ADDR_REG) {	/* DMA dram address */
	word = cop0_RegGet(1);
    } else if (addr == SP_MEM_ADDR_REG) {	/* DMA sp mem address */
	word = cop0_RegGet(0);
    } else if (addr == SP_RD_LEN_REG) {		/* DMA read length */
	word = cop0_RegGet(2);
    } else if (addr == SP_WR_LEN_REG) {		/* DMA write length */
	word = cop0_RegGet(3);
    } else if (addr == SP_STATUS_REG) {		/* SP status (read) */

	word = rsp_controlReg;

    } else if (addr == SP_DMA_FULL_REG) {	/* SP DMA full */
	word = cop0_RegGet(5);
    } else if (addr == SP_DMA_BUSY_REG) {	/* SP DMA busy */
	word = cop0_RegGet(6);
    } else if (addr == SP_SEMAPHORE_REG) {	/* SP semaphore (read) */
	word = cop0_RegGet(7);

    } else if (addr == SP_PC_REG) {	/* SP pc */
	word = (rsp_programCounter & 0x00000fff);
    } else if (addr == SP_IBIST_REG) {	/* SP IMEM BIST status */
    }

    return(word);
}