reality.makefile
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#!smake
#
# This makefile has rules for making both the executables
# which make up the simulator, and for running test cases.
#
#
COMMONPREF=rcp
#PRDEPTH = ../../..
PRDEPTH = $(ROOT)/PR
REALITY_SIM = $(PRDEPTH)/hw/chip/sim
REGRESSION = $(PRDEPTH)/rspsim/vuregre/regression
include $(PRDEPTH)/PRdefs
#override GVCSOPTS
GVCSOPTS = -l vcs.log -M -Mupdate -Mmakep=pmake \
-CC "-Wab,-big_got -Wab,-dwalign" -lgl -limage
#
# Tools
#
SIMV = LD_LIBRARY_PATH=$(VCSDIR)/lib simv -q
#
# Directories
#
#
# C Sources
#
# Header file Directories
#
LCINCS =
GCINCS =
#
# Compiler options
#
OPTIMIZER = -g
LCOPTS = -fullwarn
#
# Verilog compiler options
#
LVCSOPTS = \
-y . \
-y $(PRDEPTH)/hw/chip/lib/verilog/pads \
-y $(PRDEPTH)/hw/chip/sim \
-y $(PRDEPTH)/hw/chip/rcp/src \
-y $(PRDEPTH)/hw/chip/rcp/rdp/src \
-y $(PRDEPTH)/hw/chip/rcp/ri/src \
-y $(PRDEPTH)/hw/chip/rcp/rsp/src \
-y $(PRDEPTH)/hw/chip/rcp/ar/src \
-y $(PRDEPTH)/hw/chip/rcp/mi/src \
-y $(PRDEPTH)/hw/chip/rcp/vi/src \
-y $(PRDEPTH)/hw/chip/rcp/ai/src \
-y $(PRDEPTH)/hw/chip/rcp/pi/src \
-y $(PRDEPTH)/hw/chip/rcp/si/src \
-y $(PRDEPTH)/hw/chip/rcp/cs/src \
-y $(PRDEPTH)/hw/chip/rcp/ew/src \
-y $(PRDEPTH)/hw/chip/rcp/ep/src \
-y $(PRDEPTH)/hw/chip/rcp/cv/src \
-y $(PRDEPTH)/hw/chip/rcp/st/src \
-y $(PRDEPTH)/hw/chip/rcp/tc/src \
-y $(PRDEPTH)/hw/chip/rcp/tm/src \
-y $(PRDEPTH)/hw/chip/rcp/tf/src \
-y $(PRDEPTH)/hw/chip/rcp/cc/src \
-y $(PRDEPTH)/hw/chip/rcp/bl/src \
-y $(PRDEPTH)/hw/chip/rcp/at/src \
-y $(PRDEPTH)/hw/chip/rcp/bl/src \
-y $(PRDEPTH)/hw/chip/rcp/ms/src \
-y $(PRDEPTH)/hw/chip/rcp/rsp/src \
-y $(PRDEPTH)/hw/chip/rcp/su/src \
-y $(PRDEPTH)/hw/chip/rcp/vu/src \
-y $(PRDEPTH)/hw/chip/rcp/ls/src \
-y $(PRDEPTH)/hw/chip/rcp/is/src \
-y $(PRDEPTH)/hw/chip/rcp/io/src \
-y $(PRDEPTH)/hw/chip/rcp/dm/src \
-y $(PRDEPTH)/hw/chip/rcp/sb/src \
-y $(PRDEPTH)/hw/chip/rcp/su/fixes \
-y $(PRDEPTH)/hw/chip/rcp/div/src \
-y $(PRDEPTH)/hw/chip/rcp/tst/src \
-y $(PRDEPTH)/hw/chip/lib/verilog/dp \
-y $(PRDEPTH)/hw/chip/lib/verilog/stdcell \
-y $(PRDEPTH)/hw/chip/lib/verilog/ram \
-y $(PRDEPTH)/hw/chip/lib/verilog/user \
-y $(PRDEPTH)/hw/chip/lib/verilog/rac/behavioral \
-y $(PRDEPTH)/hw/chip/lib/verilog/udp \
-y $(PRDEPTH)/hw/chip/lib/verilog/rdram/behavioral \
-y $(PRDEPTH)/hw/chip/lib/verilog/pif \
+libext+.v+.vzd+.vmd \
+incdir+$(PRDEPTH)/hw/chip/rcp/inc \
+incdir+$(PRDEPTH)/hw/chip/rcp/su/src \
+incdir+$(PRDEPTH)/hw/chip/rcp/vu/src \
+incdir+$(PRDEPTH)/hw/chip/rcp/ms/src \
+incdir+$(PRDEPTH)/hw/chip/sim \
+incdir+$(REGRESSION) \
-Mdir=./designc \
-l vcs.log
#
# Default Targets
#
# Default Targets
#
TESTS = simv
default install: $(TESTS)
$(COMMONTARGS): $(COMMONPREF)$$@
$(SUBDIRS_MAKERULE)
#
# SGI/Project Reality Common Rules
#
include $(PRDEPTH)/PRrules
#
# Compile Verilog processes
#
simv: $(REALITY_SIM)/reality.v $(REGRESSION)/rsp_ctrace.v $(_FORCE)
VCS_RUNTIME=$(VCSDIR)/lib/libvcs.so \
$(VCS) $(VCSOPTS) -o $@ $(REALITY_SIM)/reality.v \
$(REGRESSION)/reality_rsp_regr.h \
$(REGRESSION)/rsp_ctrace.v \
rsp_tests.v \
simenv : $(_FORCE)
echo " setenv LD_LIBRARY_PATH=$(VCSDIR)/lib >> Setenv"
echo "enter command% source Setenv"