sp_mem_tests.v
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`timescale 1ns / 10ps
`define RSP_DMEM_BASE 32'h04000000
`define RSP_IMEM_BASE 32'h04001000
`define MEM_SIZE 4096
module sp_mem_tests;
integer i;
integer msb;
reg [31:0] write_data;
initial begin
if ($test$plusargs("imempat_5s_l")) begin
init_mem_tests;
mem_pattern (`RSP_IMEM_BASE,512,32'h55555555);
end
if ($test$plusargs("imempat_5s_h")) begin
init_mem_tests;
mem_pattern (`RSP_IMEM_BASE+(512*4),512,32'h55555555);
end
if ($test$plusargs("imempat_as_l")) begin
init_mem_tests;
mem_pattern (`RSP_IMEM_BASE,512,32'haaaaaaaa);
end
if ($test$plusargs("imempat_as_h")) begin
init_mem_tests;
mem_pattern (`RSP_IMEM_BASE+(512*4),512,32'haaaaaaaa);
end
if ($test$plusargs("dmempat_5s_l")) begin
init_mem_tests;
mem_pattern (`RSP_DMEM_BASE,512,32'h55555555);
end
if ($test$plusargs("dmempat_5s_h")) begin
init_mem_tests;
mem_pattern (`RSP_DMEM_BASE+(512*4),512,32'h55555555);
end
if ($test$plusargs("dmempat_as_l")) begin
init_mem_tests;
mem_pattern (`RSP_DMEM_BASE,512,32'haaaaaaaa);
end
if ($test$plusargs("dmempat_as_h")) begin
init_mem_tests;
mem_pattern (`RSP_DMEM_BASE+(512*4),512,32'haaaaaaaa);
end
if ($test$plusargs("imem1_l")) begin
init_mem_tests;
marching_1 (`RSP_IMEM_BASE, 512, 32'h1);
end
if ($test$plusargs("imem1_h")) begin
init_mem_tests;
marching_1 (`RSP_IMEM_BASE+(512*4), 512, 32'h2);
end
if ($test$plusargs("dmem1_l")) begin
init_mem_tests;
marching_1 (`RSP_DMEM_BASE, 512, 32'h1);
end
if ($test$plusargs("dmem1_h")) begin
init_mem_tests;
marching_1 (`RSP_DMEM_BASE+(512*4), 512, 32'h2);
end
$finish;
end
task init_mem_tests;
begin
#16
reality.r4200b_0.test_selected = 1;
wait(`SYSTEM_READY);
repeat (4) @(posedge reality.rcp_0.clock);
$display ("config RDRAM starts");
reality.r4200b_0.config_rdram;
$display ("config RDRAM ends");
end
endtask
task mem_pattern;
input [31:0] start_address;
input [15:0] lenth;
input [31:0] pattern;
begin
repeat (4) @(posedge reality.rcp_0.clock);
write_data = pattern;
for (i=start_address; i<start_address + (lenth*4); i=i+4) begin
$display("Writing Mem[0x%x] <- %h", i, write_data);
reality.r4200b_0.write_word(i, 3, write_data);
end
for (i=start_address; i<start_address + (lenth*4); i=i+4) begin
$display("Reading Mem[0x%x]", i);
reality.r4200b_0.read_word(i, 3);
if (reality.r4200b_0.data[0]!==pattern)
$display ("ERROR: RRDATA from memory MISCOMPARED, Address = %h, Read Data = %h, Expected Data = %h",
i, reality.r4200b_0.data[0],pattern);
end
end
endtask
//
// Fill Mem with Marching 1
//
task marching_1;
input [31:0] start_address;
input [15:0] lenth;
input [31:0] pattern;
begin
repeat (4) @(posedge reality.rcp_0.clock);
write_data = pattern;
for (i=start_address; i<start_address + (lenth*4); i=i+4) begin
reality.r4200b_0.write_word(i, 3, write_data);
write_data = (write_data == 32'h40000000) ? 1 : (write_data << 1);
end
write_data = pattern;
for (i=start_address; i<start_address + (lenth*4); i=i+4) begin
reality.r4200b_0.read_word(i, 3);
if (reality.r4200b_0.data[0]!==write_data)
$display ("ERROR: RRDATA from memory MISCOMPARED, Address = %h, Read Data = %h, Expected Data = %h",
i, reality.r4200b_0.data[0], write_data);
write_data = (write_data == 32'h40000000) ? 1 : (write_data << 1);
end
end
endtask
endmodule